Encoder, a decoder, and corresponding methods for transform process in video coding

ABSTRACT

The present disclosure provides methods and devices. A video method of coding implemented by a decoding device, comprising: when a prediction mode of a current coding block is intra prediction, and the current coding block is processed by using Intra sub-partition coding mode, determining whether a width of a current transform block is larger than or equal to a first threshold or not, and whether the width of the current transform block is smaller than or equal to a second threshold or not, the current transform block corresponding to the current coding block; when the width of the current transform block is larger than or equal to the first threshold and the width of the current transform block is smaller than or equal to the second threshold, performing transform process on the current transform block, wherein a transform core based on DST 7 is used on horizontal direction transform.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of International Application No. PCT/CN2020/074780, filed on Feb. 12, 2020, which claims the priority to U.S. Provisional Patent Application No. 62/813,136, filed Mar. 3, 2019, and U.S. Provisional Patent Application No. 62/815,293, filed Mar. 7, 2019. The disclosures of the aforementioned patent applications are hereby incorporated by reference in their entireties.

TECHNICAL FIELD

Embodiments of the present application (disclosure) generally relate to the field of picture or video processing, and more particularly to the transform process.

BACKGROUND

Video coding (video encoding and decoding) is used in a wide range of digital video applications, for example broadcast digital TV, video transmission over internet and mobile networks, real-time conversational applications such as video chat, video conferencing, DVD and Blu-ray discs, video content acquisition and editing systems, and camcorders of security applications.

The amount of video data needed to depict even a relatively short video can be substantial, which may result in difficulties when the data is to be streamed or otherwise communicated across a communications network with limited bandwidth capacity. Thus, video data is generally compressed before being communicated across modem day telecommunications networks. The size of a video could also be an issue when the video is stored on a storage device because memory resources may be limited. Video compression devices often use software and/or hardware at the source to code the video data prior to transmission or storage, thereby decreasing the quantity of data needed to represent digital video images. The compressed data is then received at the destination by a video decompression device that decodes the video data. With limited network resources and ever increasing demands of higher video quality, improved compression and decompression techniques that improve compression ratio with little to no sacrifice in picture quality are desirable.

SUMMARY

Embodiments of the present application provide apparatuses and methods for encoding and decoding according to the independent claims.

The foregoing and other objects are achieved by the subject matter of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

The first aspect of the disclosure discloses a method of coding implemented by a decoding device, comprising: when a prediction mode of a current coding block is intra prediction, and the current coding block is processed by using Intra sub-partition, ISP, coding mode, determining whether a width of a current transform block is larger than or equal to a first threshold or not, and whether the width of the current transform block is smaller than or equal to a second threshold or not, the current transform block is corresponded to the current coding block; when the width of the current transform block is larger than or equal to the first threshold and the width of the current transform block is smaller than or equal to the second threshold, performing transform process on the current transform block, wherein a transform core DST 7 is used on horizontal direction transform.

In one possible implementation, wherein the method further comprises:

when the width of the current transform block is smaller than the first threshold, or when the width of the current transform block is larger than the second threshold, performing transform process on the current transform block, wherein the transform process a transform core DCT2 is used on horizontal transform.

In one possible implementation, wherein the method further comprises:

obtaining a value of a syntax for the current coding block, wherein the value of the syntax for the current coding block is used to indicate the prediction mode of the current coding block is intra prediction.

In one possible implementation, wherein the value of the syntax for the current coding block is not indicate a specify prediction mode of the current coding block.

The second aspect of the disclosure discloses a method of coding implemented by a decoding device, comprising: when a prediction mode of a current coding block is intra prediction, and the current coding block is processed by using Intra sub-partition, ISP, coding mode, determining whether a height of a current transform block is larger than or equal to a third threshold or not, and whether the height of the current transform block is smaller than or equal to a fourth threshold or not, the current transform block is corresponded to the current coding block; when the height of the current transform block is larger than or equal to the third threshold and smaller than or equal to the fourth threshold, performing transform process on the current transform block, wherein a transform core DST 7 is used on vertical direction transform.

In one possible implementation, wherein the method further comprises: when the height of the current transform block is smaller than the third threshold, or when the height of the current transform block is larger than the fourth threshold,

performing transform process on the current transform block, wherein a transform core DCT 2 is used on vertical direction transform.

In one possible implementation, wherein the method further comprises:

obtaining a value of a syntax for the current coding block, wherein the value of the syntax for the current coding block is used to indicate the prediction mode of the current coding block is intra prediction.

In one possible implementation, wherein the value of the syntax for the current coding block is not indicate a specify prediction mode of the current coding block.

The third aspect of the disclosure discloses a method of coding implemented by a decoding device, comprising: when a Multiple Transform Selection, MTS, scheme is unavailable for a current coding block, determining whether a width of a current transform block is larger than or equal to a first threshold or not, and whether the width of the current transform block is smaller than or equal to a second threshold or not, the current transform block is corresponded to the current coding block; when the width of the current transform block is larger than or equal to the first threshold and smaller than or equal to the second threshold, performing transform process on the current transform block, wherein a transform core DST 7 is used on horizontal direction transform.

In one possible implementation, wherein the method further comprises: when the width of the current transform block is smaller than the first threshold, or when the width of the current transform block is larger than the second threshold,

performing transform process on the current transform block, wherein a transform core DCT 2 is used on horizontal direction transform.

The fourth aspect of the disclosure discloses a method of coding implemented by a decoding device, comprising: when a Multiple Transform Selection, MTS, scheme is unavailable for a current coding block, determining whether a height of a current transform block is larger than or equal to a third threshold or not, and whether the height of the current transform block is smaller than or equal to a fourth threshold or not, the current transform block is corresponded to the current coding block; when the height of the current transform block is larger than or equal to the third threshold and smaller than or equal to the fourth threshold, performing transform process on the current transform block, wherein a transform core DST 7 is used on vertical direction transform.

In one possible implementation, wherein the method further comprises:

when the height of the current transform block is smaller than the third threshold, or when the height of the current transform block is larger than the fourth threshold,

performing transform process on the current transform block, wherein a transform core DCT 2 is used on vertical direction transform.

The fifth aspect of the disclosure discloses a method of coding implemented by a decoding device, comprising:

when a Multiple Transform Selection, MTS, scheme is unavailable for a current coding block, a width of a current transform block is larger than or equal to a first threshold and smaller than or equal to a second threshold,

and a height of the current transform block is larger than or equal to a third threshold and smaller than or equal to a fourth threshold, the current transform block is corresponded to the current coding block,

determining whether a value of a ratio of block width and height corresponding to the current transform block is larger than a fifth threshold or not,

when the value of the ratio of block width and height is smaller than or equal to the fifth threshold,

a transform core DST 7 is used for horizontal and vertical transform of the current transform block.

In one possible implementation, wherein the method further comprises:

when the value of the ratio of block width and height is larger than the fifth threshold, and the width of the current transform block is smaller than the height of the current transform block,

a transform core DST 7 is used for horizontal transform of the current transform block and a transform core DCT 2 is used for vertical transform of the current transform block.

In one possible implementation, wherein the method further comprises:

when the value of the ratio of block width and height is larger than the fifth threshold, and the width of the current transform block is larger than the height of the current transform block,

a transform core DCT 2 is used for horizontal transform of the current transform block and a transform core DST 7 is used for vertical transform of the current transform block.

The sixth aspect of the disclosure discloses a decoder (30) comprising processing circuitry for carrying out any one of the above method embodiments.

The seventh aspect of the disclosure discloses a computer program product comprising a program code for performing the method according to any one of the above method embodiments.

The eighth aspect of the disclosure discloses a decoder, comprising:

one or more processors; and a non-transitory computer-readable storage medium coupled to the processors and storing programming for execution by the processors, wherein the programming, when executed by the processors, configures the decoder to carry out the method according to any one of the above method embodiments.

Details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description, drawings, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following embodiments of the invention are described in more detail with reference to the attached figures and drawings, in which:

FIG. 1A is a block diagram showing an example of a video coding system configured to implement embodiments of the invention;

FIG. 1B is a block diagram showing another example of a video coding system configured to implement embodiments of the invention;

FIG. 2 is a block diagram showing an example of a video encoder configured to implement embodiments of the invention;

FIG. 3 is a block diagram showing an example structure of a video decoder configured to implement embodiments of the invention;

FIG. 4 is a block diagram illustrating an example of an encoding apparatus or a decoding apparatus;

FIG. 5 is a block diagram illustrating another example of an encoding apparatus or a decoding apparatus;

FIG. 6 shows an example of the division of 4×8 and 8×4 blocks.

FIG. 7 shows an example of the division of blocks except 4×8, 8×4 and 4×4 blocks.

FIG. 8 is a block diagram showing an example structure of a content supply system 3100 which realizes a content delivery service.

FIG. 9 is a block diagram showing a structure of an example of a terminal device.

In the following identical reference signs refer to identical or at least functionally equivalent features if not explicitly specified otherwise.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In the following description, reference is made to the accompanying figures, which form part of the disclosure, and which show, by way of illustration, specific aspects of embodiments of the invention or specific aspects in which embodiments of the present invention may be used. It is understood that embodiments of the invention may be used in other aspects and comprise structural or logical changes not depicted in the figures. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the disclosure is defined by the appended claims.

For instance, it is understood that a disclosure in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if one or a plurality of specific method steps are described, a corresponding device may include one or a plurality of units, e.g. functional units, to perform the described one or plurality of method steps (e.g. one unit performing the one or plurality of steps, or a plurality of units each performing one or more of the plurality of steps), even if such one or more units are not explicitly described or illustrated in the figures. On the other hand, for example, if a specific apparatus is described based on one or a plurality of units, e.g. functional units, a corresponding method may include one step to perform the functionality of the one or plurality of units (e.g. one step performing the functionality of the one or plurality of units, or a plurality of steps each performing the functionality of one or more of the plurality of units), even if such one or plurality of steps are not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary embodiments and/or aspects described herein may be combined with each other, unless specifically noted otherwise.

Video coding typically refers to the processing of a sequence of pictures, which form the video or video sequence. Instead of the term “picture” the term “frame” or “image” may be used as synonyms in the field of video coding. Video coding (or coding in general) comprises two parts video encoding and video decoding. Video encoding is performed at the source side, typically comprising processing (e.g. by compression) the original video pictures to reduce the amount of data required for representing the video pictures (for more efficient storage and/or transmission). Video decoding is performed at the destination side and typically comprises the inverse processing compared to the encoder to reconstruct the video pictures. Embodiments referring to “coding” of video pictures (or pictures in general) shall be understood to relate to “encoding” or “decoding” of video pictures or respective video sequences. The combination of the encoding part and the decoding part is also referred to as CODEC (Coding and Decoding).

In case of lossless video coding, the original video pictures can be reconstructed, i.e. the reconstructed video pictures have the same quality as the original video pictures (assuming no transmission loss or other data loss during storage or transmission). In case of lossy video coding, further compression, e.g. by quantization, is performed, to reduce the amount of data representing the video pictures, which cannot be completely reconstructed at the decoder, i.e. the quality of the reconstructed video pictures is lower or worse compared to the quality of the original video pictures.

Several video coding standards belong to the group of “lossy hybrid video codecs” (i.e. combine spatial and temporal prediction in the sample domain and 2D transform coding for applying quantization in the transform domain). Each picture of a video sequence is typically partitioned into a set of non-overlapping blocks and the coding is typically performed on a block level. In other words, at the encoder the video is typically processed, i.e. encoded, on a block (video block) level, e.g. by using spatial (intra picture) prediction and/or temporal (inter picture) prediction to generate a prediction block, subtracting the prediction block from the current block (block currently processed/to be processed) to obtain a residual block, transforming the residual block and quantizing the residual block in the transform domain to reduce the amount of data to be transmitted (compression), whereas at the decoder the inverse processing compared to the encoder is applied to the encoded or compressed block to reconstruct the current block for representation. Furthermore, the encoder duplicates the decoder processing loop such that both will generate identical predictions (e.g. intra- and inter predictions) and/or re-constructions for processing, i.e. coding, the subsequent blocks.

In the following embodiments of a video coding system 10, a video encoder 20 and a video decoder 30 are described based on FIGS. 1 to 3.

FIG. 1A is a schematic block diagram illustrating an example coding system 10, e.g. a video coding system 10 (or short coding system 10) that may utilize techniques of this present application. Video encoder 20 (or short encoder 20) and video decoder 30 (or short decoder 30) of video coding system 10 represent examples of devices that may be configured to perform techniques in accordance with various examples described in the present application.

As shown in FIG. 1A, the coding system 10 comprises a source device 12 configured to provide encoded picture data 21 e.g. to a destination device 14 for decoding the encoded picture data 13.

The source device 12 comprises an encoder 20, and may additionally, i.e. optionally, comprise a picture source 16, a pre-processor (or pre-processing unit) 18, e.g. a picture pre-processor 18, and a communication interface or communication unit 22.

The picture source 16 may comprise or be any kind of picture capturing device, for example a camera for capturing a real-world picture, and/or any kind of a picture generating device, for example a computer-graphics processor for generating a computer animated picture, or any kind of other device for obtaining and/or providing a real-world picture, a computer generated picture (e.g. a screen content, a virtual reality (VR) picture) and/or any combination thereof (e.g. an augmented reality (AR) picture). The picture source may be any kind of memory or storage storing any of the aforementioned pictures.

In distinction to the pre-processor 18 and the processing performed by the pre-processing unit 18, the picture or picture data 17 may also be referred to as raw picture or raw picture data 17.

Pre-processor 18 is configured to receive the (raw) picture data 17 and to perform pre-processing on the picture data 17 to obtain a pre-processed picture 19 or pre-processed picture data 19. Pre-processing performed by the pre-processor 18 may, e.g., comprise trimming, color format conversion (e.g. from RGB to YCbCr), color correction, or de-noising. It can be understood that the pre-processing unit 18 may be optional component.

The video encoder 20 is configured to receive the pre-processed picture data 19 and provide encoded picture data 21 (further details will be described below, e.g., based on FIG. 2).

Communication interface 22 of the source device 12 may be configured to receive the encoded picture data 21 and to transmit the encoded picture data 21 (or any further processed version thereof) over communication channel 13 to another device, e.g. the destination device 14 or any other device, for storage or direct reconstruction.

The destination device 14 comprises a decoder 30 (e.g. a video decoder 30), and may additionally, i.e. optionally, comprise a communication interface or communication unit 28, a post-processor 32 (or post-processing unit 32) and a display device 34.

The communication interface 28 of the destination device 14 is configured receive the encoded picture data 21 (or any further processed version thereof), e.g. directly from the source device 12 or from any other source, e.g. a storage device, e.g. an encoded picture data storage device, and provide the encoded picture data 21 to the decoder 30.

The communication interface 22 and the communication interface 28 may be configured to transmit or receive the encoded picture data 21 or encoded data 13 via a direct communication link between the source device 12 and the destination device 14, e.g. a direct wired or wireless connection, or via any kind of network, e.g. a wired or wireless network or any combination thereof, or any kind of private and public network, or any kind of combination thereof.

The communication interface 22 may be, e.g., configured to package the encoded picture data 21 into an appropriate format, e.g. packets, and/or process the encoded picture data using any kind of transmission encoding or processing for transmission over a communication link or communication network.

The communication interface 28, forming the counterpart of the communication interface 22, may be, e.g., configured to receive the transmitted data and process the transmission data using any kind of corresponding transmission decoding or processing and/or de-packaging to obtain the encoded picture data 21.

Both, communication interface 22 and communication interface 28 may be configured as unidirectional communication interfaces as indicated by the arrow for the communication channel 13 in FIG. 1A pointing from the source device 12 to the destination device 14, or bi-directional communication interfaces, and may be configured, e.g. to send and receive messages, e.g. to set up a connection, to acknowledge and exchange any other information related to the communication link and/or data transmission, e.g. encoded picture data transmission.

The decoder 30 is configured to receive the encoded picture data 21 and provide decoded picture data 31 or a decoded picture 31 (further details will be described below, e.g., based on FIG. 3 or FIG. 5).

The post-processor 32 of destination device 14 is configured to post-process the decoded picture data 31 (also called reconstructed picture data), e.g. the decoded picture 31, to obtain post-processed picture data 33, e.g. a post-processed picture 33. The post-processing performed by the post-processing unit 32 may comprise, e.g. color format conversion (e.g. from YCbCr to RGB), color correction, trimming, or re-sampling, or any other processing, e.g. for preparing the decoded picture data 31 for display, e.g. by display device 34.

The display device 34 of the destination device 14 is configured to receive the post-processed picture data 33 for displaying the picture, e.g. to a user or viewer. The display device 34 may be or comprise any kind of display for representing the reconstructed picture, e.g. an integrated or external display or monitor. The displays may, e.g. comprise liquid crystal displays (LCD), organic light emitting diodes (OLED) displays, plasma displays, projectors, micro LED displays, liquid crystal on silicon (LCoS), digital light processor (DLP) or any kind of other display.

Although FIG. 1A depicts the source device 12 and the destination device 14 as separate devices, embodiments of devices may also comprise both or both functionalities, the source device 12 or corresponding functionality and the destination device 14 or corresponding functionality. In such embodiments the source device 12 or corresponding functionality and the destination device 14 or corresponding functionality may be implemented using the same hardware and/or software or by separate hardware and/or software or any combination thereof.

As will be apparent for the skilled person based on the description, the existence and (exact) split of functionalities of the different units or functionalities within the source device 12 and/or destination device 14 as shown in FIG. 1A may vary depending on the actual device and application.

The encoder 20 (e.g. a video encoder 20) or the decoder 30 (e.g. a video decoder 30) or both encoder 20 and decoder 30 may be implemented via processing circuitry as shown in FIG. 1B, such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, hardware, video coding dedicated or any combinations thereof. The encoder 20 may be implemented via processing circuitry 46 to embody the various modules as discussed with respect to encoder 20 of FIG. 2 and/or any other encoder system or subsystem described herein. The decoder 30 may be implemented via processing circuitry 46 to embody the various modules as discussed with respect to decoder 30 of FIG. 3 and/or any other decoder system or subsystem described herein. The processing circuitry may be configured to perform the various operations as discussed later. As shown in FIG. 5, if the techniques are implemented partially in software, a device may store instructions for the software in a suitable, non-transitory computer-readable storage medium and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Either of video encoder 20 and video decoder 30 may be integrated as part of a combined encoder/decoder (CODEC) in a single device, for example, as shown in FIG. 1B.

Source device 12 and destination device 14 may comprise any of a wide range of devices, including any kind of handheld or stationary devices, e.g. notebook or laptop computers, mobile phones, smart phones, tablets or tablet computers, cameras, desktop computers, set-top boxes, televisions, display devices, digital media players, video gaming consoles, video streaming devices (such as content services servers or content delivery servers), broadcast receiver device, broadcast transmitter device, or the like and may use no or any kind of operating system. In some cases, the source device 12 and the destination device 14 may be equipped for wireless communication. Thus, the source device 12 and the destination device 14 may be wireless communication devices.

In some cases, video coding system 10 illustrated in FIG. 1A is merely an example and the techniques of the present application may apply to video coding settings (e.g., video encoding or video decoding) that do not necessarily include any data communication between the encoding and decoding devices. In other examples, data is retrieved from a local memory, streamed over a network, or the like. A video encoding device may encode and store data to memory, and/or a video decoding device may retrieve and decode data from memory. In some examples, the encoding and decoding is performed by devices that do not communicate with one another, but simply encode data to memory and/or retrieve and decode data from memory.

For convenience of description, embodiments of the invention are described herein, for example, by reference to High-Efficiency Video Coding (HEVC) or to the reference software of Versatile Video coding (VVC), the next generation video coding standard developed by the Joint Collaboration Team on Video Coding (JCT-VC) of ITU-T Video Coding Experts Group (VCEG) and ISO/IEC Motion Picture Experts Group (MPEG). One of ordinary skill in the art will understand that embodiments of the invention are not limited to HEVC or VVC.

Encoder and Encoding Method

FIG. 2 shows a schematic block diagram of an example video encoder 20 that is configured to implement the techniques of the present application. In the example of FIG. 2, the video encoder 20 comprises an input 201 (or input interface 201), a residual calculation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, and inverse transform processing unit 212, a reconstruction unit 214, a loop filter unit 220, a decoded picture buffer (DPB) 230, a mode selection unit 260, an entropy encoding unit 270 and an output 272 (or output interface 272). The mode selection unit 260 may include an inter prediction unit 244, an intra prediction unit 254 and a partitioning unit 262. Inter prediction unit 244 may include a motion estimation unit and a motion compensation unit (not shown). A video encoder 20 as shown in FIG. 2 may also be referred to as hybrid video encoder or a video encoder according to a hybrid video codec.

The residual calculation unit 204, the transform processing unit 206, the quantization unit 208, the mode selection unit 260 may be referred to as forming a forward signal path of the encoder 20, whereas the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the buffer 216, the loop filter 220, the decoded picture buffer (DPB) 230, the inter prediction unit 244 and the intra-prediction unit 254 may be referred to as forming a backward signal path of the video encoder 20, wherein the backward signal path of the video encoder 20 corresponds to the signal path of the decoder (see video decoder 30 in FIG. 3). The inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the loop filter 220, the decoded picture buffer (DPB) 230, the inter prediction unit 244 and the intra-prediction unit 254 are also referred to forming the “built-in decoder” of video encoder 20.

Pictures & Picture Partitioning (Pictures & Blocks)

The encoder 20 may be configured to receive, e.g. via input 201, a picture 17 (or picture data 17), e.g. picture of a sequence of pictures forming a video or video sequence. The received picture or picture data may also be a pre-processed picture 19 (or pre-processed picture data 19). For sake of simplicity the following description refers to the picture 17. The picture 17 may also be referred to as current picture or picture to be coded (in particular in video coding to distinguish the current picture from other pictures, e.g. previously encoded and/or decoded pictures of the same video sequence, i.e. the video sequence which also comprises the current picture).

A (digital) picture is or can be regarded as a two-dimensional array or matrix of samples with intensity values. A sample in the array may also be referred to as pixel (short form of picture element) or a pel. The number of samples in horizontal and vertical direction (or axis) of the array or picture define the size and/or resolution of the picture. For representation of color, typically three color components are employed, i.e. the picture may be represented or include three sample arrays. In RBG format or color space a picture comprises a corresponding red, green and blue sample array. However, in video coding each pixel is typically represented in a luminance and chrominance format or color space, e.g. YCbCr, which comprises a luminance component indicated by Y (sometimes also L is used instead) and two chrominance components indicated by Cb and Cr. The luminance (or short luma) component Y represents the brightness or grey level intensity (e.g. like in a grey-scale picture), while the two chrominance (or short chroma) components Cb and Cr represent the chromaticity or color information components. Accordingly, a picture in YCbCr format comprises a luminance sample array of luminance sample values (Y), and two chrominance sample arrays of chrominance values (Cb and Cr). Pictures in RGB format may be converted or transformed into YCbCr format and vice versa, the process is also known as color transformation or conversion. If a picture is monochrome, the picture may comprise only a luminance sample array. Accordingly, a picture may be, for example, an array of luma samples in monochrome format or an array of luma samples and two corresponding arrays of chroma samples in 4:2:0, 4:2:2, and 4:4:4 colour format.

Embodiments of the video encoder 20 may comprise a picture partitioning unit (not depicted in FIG. 2) configured to partition the picture 17 into a plurality of (typically non-overlapping) picture blocks 203. These blocks may also be referred to as root blocks, macro blocks (H.264/AVC) or coding tree blocks (CTB) or coding tree units (CTU) (H.265/HEVC and VVC). The picture partitioning unit may be configured to use the same block size for all pictures of a video sequence and the corresponding grid defining the block size, or to change the block size between pictures or subsets or groups of pictures, and partition each picture into the corresponding blocks.

In further embodiments, the video encoder may be configured to receive directly a block 203 of the picture 17, e.g. one, several or all blocks forming the picture 17. The picture block 203 may also be referred to as current picture block or picture block to be coded.

Like the picture 17, the picture block 203 again is or can be regarded as a two-dimensional array or matrix of samples with intensity values (sample values), although of smaller dimension than the picture 17. In other words, the block 203 may comprise, e.g., one sample array (e.g. a luma array in case of a monochrome picture 17, or a luma or chroma array in case of a color picture) or three sample arrays (e.g. a luma and two chroma arrays in case of a color picture 17) or any other number and/or kind of arrays depending on the color format applied. The number of samples in horizontal and vertical direction (or axis) of the block 203 define the size of block 203. Accordingly, a block may, for example, an M×N (M-column by N-row) array of samples, or an M×N array of transform coefficients.

Embodiments of the video encoder 20 as shown in FIG. 2 may be configured to encode the picture 17 block by block, e.g. the encoding and prediction is performed per block 203.

Embodiments of the video encoder 20 as shown in FIG. 2 may be further configured to partition and/or encode the picture by using slices (also referred to as video slices), wherein a picture may be partitioned into or encoded using one or more slices (typically non-overlapping), and each slice may comprise one or more blocks (e.g. CTUs).

Embodiments of the video encoder 20 as shown in FIG. 2 may be further configured to partition and/or encode the picture by using tile groups (also referred to as video tile groups) and/or tiles (also referred to as video tiles), wherein a picture may be partitioned into or encoded using one or more tile groups (typically non-overlapping), and each tile group may comprise, e.g. one or more blocks (e.g. CTUs) or one or more tiles, wherein each tile, e.g. may be of rectangular shape and may comprise one or more blocks (e.g. CTUs), e.g. complete or fractional blocks.

Residual Calculation

The residual calculation unit 204 may be configured to calculate a residual block 205 (also referred to as residual 205) based on the picture block 203 and a prediction block 265 (further details about the prediction block 265 are provided later), e.g. by subtracting sample values of the prediction block 265 from sample values of the picture block 203, sample by sample (pixel by pixel) to obtain the residual block 205 in the sample domain.

Transform

The transform processing unit 206 may be configured to apply a transform, e.g. a discrete cosine transform (DCT) or discrete sine transform (DST), on the sample values of the residual block 205 to obtain transform coefficients 207 in a transform domain. The transform coefficients 207 may also be referred to as transform residual coefficients and represent the residual block 205 in the transform domain.

The transform processing unit 206 may be configured to apply integer approximations of DCT/DST, such as the transforms specified for H.265/HEVC. Compared to an orthogonal DCT transform, such integer approximations are typically scaled by a certain factor. In order to preserve the norm of the residual block which is processed by forward and inverse transforms, additional scaling factors are applied as part of the transform process. The scaling factors are typically chosen based on certain constraints like scaling factors being a power of two for shift operations, bit depth of the transform coefficients, tradeoff between accuracy and implementation costs, etc. Specific scaling factors are, for example, specified for the inverse transform, e.g. by inverse transform processing unit 212 (and the corresponding inverse transform, e.g. by inverse transform processing unit 312 at video decoder 30) and corresponding scaling factors for the forward transform, e.g. by transform processing unit 206, at an encoder 20 may be specified accordingly.

Embodiments of the video encoder 20 (respectively transform processing unit 206) may be configured to output transform parameters, e.g. a type of transform or transforms, e.g. directly or encoded or compressed via the entropy encoding unit 270, so that, e.g., the video decoder 30 may receive and use the transform parameters for decoding.

Quantization

The quantization unit 208 may be configured to quantize the transform coefficients 207 to obtain quantized coefficients 209, e.g. by applying scalar quantization or vector quantization. The quantized coefficients 209 may also be referred to as quantized transform coefficients 209 or quantized residual coefficients 209.

The quantization process may reduce the bit depth associated with some or all of the transform coefficients 207. For example, an n-bit transform coefficient may be rounded down to an m-bit Transform coefficient during quantization, where n is greater than m. The degree of quantization may be modified by adjusting a quantization parameter (QP). For example for scalar quantization, different scaling may be applied to achieve finer or coarser quantization. Smaller quantization step sizes correspond to finer quantization, whereas larger quantization step sizes correspond to coarser quantization. The applicable quantization step size may be indicated by a quantization parameter (QP). The quantization parameter may for example be an index to a predefined set of applicable quantization step sizes. For example, small quantization parameters may correspond to fine quantization (small quantization step sizes) and large quantization parameters may correspond to coarse quantization (large quantization step sizes) or vice versa. The quantization may include division by a quantization step size and a corresponding and/or the inverse dequantization, e.g. by inverse quantization unit 210, may include multiplication by the quantization step size. Embodiments according to some standards, e.g. HEVC, may be configured to use a quantization parameter to determine the quantization step size. Generally, the quantization step size may be calculated based on a quantization parameter using a fixed point approximation of an equation including division. Additional scaling factors may be introduced for quantization and dequantization to restore the norm of the residual block, which might get modified because of the scaling used in the fixed point approximation of the equation for quantization step size and quantization parameter. In one example implementation, the scaling of the inverse transform and dequantization might be combined. Alternatively, customized quantization tables may be used and signaled from an encoder to a decoder, e.g. in a bitstream. The quantization is a lossy operation, wherein the loss increases with increasing quantization step sizes.

Embodiments of the video encoder 20 (respectively quantization unit 208) may be configured to output quantization parameters (QP), e.g. directly or encoded via the entropy encoding unit 270, so that, e.g., the video decoder 30 may receive and apply the quantization parameters for decoding.

Inverse Quantization

The inverse quantization unit 210 is configured to apply the inverse quantization of the quantization unit 208 on the quantized coefficients to obtain dequantized coefficients 211, e.g. by applying the inverse of the quantization scheme applied by the quantization unit 208 based on or using the same quantization step size as the quantization unit 208. The dequantized coefficients 211 may also be referred to as dequantized residual coefficients 211 and correspond—although typically not identical to the transform coefficients due to the loss by quantization—to the transform coefficients 207.

Inverse Transform

The inverse transform processing unit 212 is configured to apply the inverse transform of the transform applied by the transform processing unit 206, e.g. an inverse discrete cosine transform (DCT) or inverse discrete sine transform (DST) or other inverse transforms, to obtain a reconstructed residual block 213 (or corresponding dequantized coefficients 213) in the sample domain. The reconstructed residual block 213 may also be referred to as transform block 213.

Reconstruction

The reconstruction unit 214 (e.g. adder or summer 214) is configured to add the transform block 213 (i.e. reconstructed residual block 213) to the prediction block 265 to obtain a reconstructed block 215 in the sample domain, e.g. by adding—sample by sample—the sample values of the reconstructed residual block 213 and the sample values of the prediction block 265.

Filtering

The loop filter unit 220 (or short “loop filter” 220), is configured to filter the reconstructed block 215 to obtain a filtered block 221, or in general, to filter reconstructed samples to obtain filtered samples. The loop filter unit is, e.g., configured to smooth pixel transitions, or otherwise improve the video quality. The loop filter unit 220 may comprise one or more loop filters such as a de-blocking filter, a sample-adaptive offset (SAO) filter or one or more other filters, e.g. a bilateral filter, an adaptive loop filter (ALF), a sharpening, a smoothing filters or a collaborative filters, or any combination thereof. Although the loop filter unit 220 is shown in FIG. 2 as being an in loop filter, in other configurations, the loop filter unit 220 may be implemented as a post loop filter. The filtered block 221 may also be referred to as filtered reconstructed block 221.

Embodiments of the video encoder 20 (respectively loop filter unit 220) may be configured to output loop filter parameters (such as sample adaptive offset information), e.g. directly or encoded via the entropy encoding unit 270, so that, e.g., a decoder 30 may receive and apply the same loop filter parameters or respective loop filters for decoding.

Decoded Picture Buffer

The decoded picture buffer (DPB) 230 may be a memory that stores reference pictures, or in general reference picture data, for encoding video data by video encoder 20. The DPB 230 may be formed by any of a variety of memory devices, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. The decoded picture buffer (DPB) 230 may be configured to store one or more filtered blocks 221. The decoded picture buffer 230 may be further configured to store other previously filtered blocks, e.g. previously reconstructed and filtered blocks 221, of the same current picture or of different pictures, e.g. previously reconstructed pictures, and may provide complete previously reconstructed, i.e. decoded, pictures (and corresponding reference blocks and samples) and/or a partially reconstructed current picture (and corresponding reference blocks and samples), for example for inter prediction. The decoded picture buffer (DPB) 230 may be also configured to store one or more unfiltered reconstructed blocks 215, or in general unfiltered reconstructed samples, e.g. if the reconstructed block 215 is not filtered by loop filter unit 220, or any other further processed version of the reconstructed blocks or samples.

Mode Selection (Partitioning & Prediction)

The mode selection unit 260 comprises partitioning unit 262, inter-prediction unit 244 and intra-prediction unit 254, and is configured to receive or obtain original picture data, e.g. an original block 203 (current block 203 of the current picture 17), and reconstructed picture data, e.g. filtered and/or unfiltered reconstructed samples or blocks of the same (current) picture and/or from one or a plurality of previously decoded pictures, e.g. from decoded picture buffer 230 or other buffers (e.g. line buffer, not shown). The reconstructed picture data is used as reference picture data for prediction, e.g. inter-prediction or intra-prediction, to obtain a prediction block 265 or predictor 265.

Mode selection unit 260 may be configured to determine or select a partitioning for a current block prediction mode (including no partitioning) and a prediction mode (e.g. an intra or inter prediction mode) and generate a corresponding prediction block 265, which is used for the calculation of the residual block 205 and for the reconstruction of the reconstructed block 215.

Embodiments of the mode selection unit 260 may be configured to select the partitioning and the prediction mode (e.g. from those supported by or available for mode selection unit 260), which provide the best match or in other words the minimum residual (minimum residual means better compression for transmission or storage), or a minimum signaling overhead (minimum signaling overhead means better compression for transmission or storage), or which considers or balances both. The mode selection unit 260 may be configured to determine the partitioning and prediction mode based on rate distortion optimization (RDO), i.e. select the prediction mode which provides a minimum rate distortion. Terms like “best”, “minimum”, “optimum” etc. in this context do not necessarily refer to an overall “best”, “minimum”, “optimum”, etc. but may also refer to the fulfillment of a termination or selection criterion like a value exceeding or falling below a threshold or other constraints leading potentially to a “sub-optimum selection” but reducing complexity and processing time.

In other words, the partitioning unit 262 may be configured to partition the block 203 into smaller block partitions or sub-blocks (which form again blocks), e.g. iteratively using quad-tree-partitioning (QT), binary partitioning (BT) or triple-tree-partitioning (TT) or any combination thereof, and to perform, e.g., the prediction for each of the block partitions or sub-blocks, wherein the mode selection comprises the selection of the tree-structure of the partitioned block 203 and the prediction modes are applied to each of the block partitions or sub-blocks.

In the following the partitioning (e.g. by partitioning unit 260) and prediction processing (by inter-prediction unit 244 and intra-prediction unit 254) performed by an example video encoder 20 will be explained in more detail.

Partitioning

The partitioning unit 262 may partition (or split) a current block 203 into smaller partitions, e.g. smaller blocks of square or rectangular size. These smaller blocks (which may also be referred to as sub-blocks) may be further partitioned into even smaller partitions. This is also referred to tree-partitioning or hierarchical tree-partitioning, wherein a root block, e.g. at root tree-level 0 (hierarchy-level 0, depth 0), may be recursively partitioned, e.g. partitioned into two or more blocks of a next lower tree-level, e.g. nodes at tree-level 1 (hierarchy-level 1, depth 1), wherein these blocks may be again partitioned into two or more blocks of a next lower level, e.g. tree-level 2 (hierarchy-level 2, depth 2), etc. until the partitioning is terminated, e.g. because a termination criterion is fulfilled, e.g. a maximum tree depth or minimum block size is reached. Blocks which are not further partitioned are also referred to as leaf-blocks or leaf nodes of the tree. A tree using partitioning into two partitions is referred to as binary-tree (BT), a tree using partitioning into three partitions is referred to as ternary-tree (TT), and a tree using partitioning into four partitions is referred to as quad-tree (QT).

As mentioned before, the term “block” as used herein may be a portion, in particular a square or rectangular portion, of a picture. With reference, for example, to HEVC and VVC, the block may be or correspond to a coding tree unit (CTU), a coding unit (CU), prediction unit (PU), and transform unit (TU) and/or to the corresponding blocks, e.g. a coding tree block (CTB), a coding block (CB), a transform block (TB) or prediction block (PB).

For example, a coding tree unit (CTU) may be or comprise a CTB of luma samples, two corresponding CTBs of chroma samples of a picture that has three sample arrays, or a CTB of samples of a monochrome picture or a picture that is coded using three separate colour planes and syntax structures used to code the samples. Correspondingly, a coding tree block (CTB) may be an N×N block of samples for some value of N such that the division of a component into CTBs is a partitioning. A coding unit (CU) may be or comprise a coding block of luma samples, two corresponding coding blocks of chroma samples of a picture that has three sample arrays, or a coding block of samples of a monochrome picture or a picture that is coded using three separate colour planes and syntax structures used to code the samples. Correspondingly a coding block (CB) may be an M×N block of samples for some values of M and N such that the division of a CTB into coding blocks is a partitioning.

In embodiments, e.g., according to HEVC, a coding tree unit (CTU) may be split into CUs by using a quad-tree structure denoted as coding tree. The decision whether to code a picture area using inter-picture (temporal) or intra-picture (spatial) prediction is made at the CU level. Each CU can be further split into one, two or four PUs according to the PU splitting type. Inside one PU, the same prediction process is applied and the relevant information is transmitted to the decoder on a PU basis. After obtaining the residual block by applying the prediction process based on the PU splitting type, a CU can be partitioned into transform units (TUs) according to another quadtree structure similar to the coding tree for the CU.

In embodiments, e.g., according to the latest video coding standard currently in development, which is referred to as Versatile Video Coding (VVC), a combined Quad-tree and binary tree (QTBT) partitioning is for example used to partition a coding block. In the QTBT block structure, a CU can have either a square or rectangular shape. For example, a coding tree unit (CTU) is first partitioned by a quadtree structure. The quadtree leaf nodes are further partitioned by a binary tree or ternary (or triple) tree structure. The partitioning tree leaf nodes are called coding units (CUs), and that segmentation is used for prediction and transform processing without any further partitioning. This means that the CU, PU and TU have the same block size in the QTBT coding block structure. In parallel, multiple partition, for example, triple tree partition may be used together with the QTBT block structure.

In one example, the mode selection unit 260 of video encoder 20 may be configured to perform any combination of the partitioning techniques described herein.

As described above, the video encoder 20 is configured to determine or select the best or an optimum prediction mode from a set of (e.g. pre-determined) prediction modes. The set of prediction modes may comprise, e.g., intra-prediction modes and/or inter-prediction modes.

Intra-Prediction

The set of intra-prediction modes may comprise 35 different intra-prediction modes, e.g. non-directional modes like DC (or mean) mode and planar mode, or directional modes, e.g. as defined in HEVC, or may comprise 67 different intra-prediction modes, e.g. non-directional modes like DC (or mean) mode and planar mode, or directional modes, e.g. as defined for VVC.

The intra-prediction unit 254 is configured to use reconstructed samples of neighboring blocks of the same current picture to generate an intra-prediction block 265 according to an intra-prediction mode of the set of intra-prediction modes.

The intra prediction unit 254 (or in general the mode selection unit 260) is further configured to output intra-prediction parameters (or in general information indicative of the selected intra prediction mode for the block) to the entropy encoding unit 270 in form of syntax elements 266 for inclusion into the encoded picture data 21, so that, e.g., the video decoder 30 may receive and use the prediction parameters for decoding.

Inter-Prediction

The set of (or possible) inter-prediction modes depends on the available reference pictures (i.e. previous at least partially decoded pictures, e.g. stored in DBP 230) and other inter-prediction parameters, e.g. whether the whole reference picture or only a part, e.g. a search window area around the area of the current block, of the reference picture is used for searching for a best matching reference block, and/or e.g. whether pixel interpolation is applied, e.g. half/semi-pel and/or quarter-pel interpolation, or not.

Additional to the above prediction modes, skip mode and/or direct mode may be applied.

The inter prediction unit 244 may include a motion estimation (ME) unit and a motion compensation (MC) unit (both not shown in FIG. 2). The motion estimation unit may be configured to receive or obtain the picture block 203 (current picture block 203 of the current picture 17) and a decoded picture 231, or at least one or a plurality of previously reconstructed blocks, e.g. reconstructed blocks of one or a plurality of other/different previously decoded pictures 231, for motion estimation. E.g. a video sequence may comprise the current picture and the previously decoded pictures 231, or in other words, the current picture and the previously decoded pictures 231 may be part of or form a sequence of pictures forming a video sequence.

The encoder 20 may, e.g., be configured to select a reference block from a plurality of reference blocks of the same or different pictures of the plurality of other pictures and provide a reference picture (or reference picture index) and/or an offset (spatial offset) between the position (x, y coordinates) of the reference block and the position of the current block as inter prediction parameters to the motion estimation unit. This offset is also called motion vector (MV).

The motion compensation unit is configured to obtain, e.g. receive, an inter prediction parameter and to perform inter prediction based on or using the inter prediction parameter to obtain an inter prediction block 265. Motion compensation, performed by the motion compensation unit, may involve fetching or generating the prediction block based on the motion/block vector determined by motion estimation, possibly performing interpolations to sub-pixel precision. Interpolation filtering may generate additional pixel samples from known pixel samples, thus potentially increasing the number of candidate prediction blocks that may be used to code a picture block. Upon receiving the motion vector for the PU of the current picture block, the motion compensation unit may locate the prediction block to which the motion vector points in one of the reference picture lists.

The motion compensation unit may also generate syntax elements associated with the blocks and video slices for use by video decoder 30 in decoding the picture blocks of the video slice. In addition or as an alternative to slices and respective syntax elements, tile groups and/or tiles and respective syntax elements may be generated or used.

Entropy Coding

The entropy encoding unit 270 is configured to apply, for example, an entropy encoding algorithm or scheme (e.g. a variable length coding (VLC) scheme, an context adaptive VLC scheme (CAVLC), an arithmetic coding scheme, a binarization, a context adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding or another entropy encoding methodology or technique) or bypass (no compression) on the quantized coefficients 209, inter prediction parameters, intra prediction parameters, loop filter parameters and/or other syntax elements to obtain encoded picture data 21 which can be output via the output 272, e.g. in the form of an encoded bitstream 21, so that, e.g., the video decoder 30 may receive and use the parameters for decoding. The encoded bitstream 21 may be transmitted to video decoder 30, or stored in a memory for later transmission or retrieval by video decoder 30.

Other structural variations of the video encoder 20 can be used to encode the video stream. For example, a non-transform based encoder 20 can quantize the residual signal directly without the transform processing unit 206 for certain blocks or frames. In another implementation, an encoder 20 can have the quantization unit 208 and the inverse quantization unit 210 combined into a single unit.

Decoder and Decoding Method

FIG. 3 shows an example of a video decoder 30 that is configured to implement the techniques of this present application. The video decoder 30 is configured to receive encoded picture data 21 (e.g. encoded bitstream 21), e.g. encoded by encoder 20, to obtain a decoded picture 331. The encoded picture data or bitstream comprises information for decoding the encoded picture data, e.g. data that represents picture blocks of an encoded video slice (and/or tile groups or tiles) and associated syntax elements.

In the example of FIG. 3, the decoder 30 comprises an entropy decoding unit 304, an inverse quantization unit 310, an inverse transform processing unit 312, a reconstruction unit 314 (e.g. a summer 314), a loop filter 320, a decoded picture buffer (DBP) 330, a mode application unit 360, an inter prediction unit 344 and an intra prediction unit 354. Inter prediction unit 344 may be or include a motion compensation unit. Video decoder 30 may, in some examples, perform a decoding pass generally reciprocal to the encoding pass described with respect to video encoder 100 from FIG. 2.

As explained with regard to the encoder 20, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214 the loop filter 220, the decoded picture buffer (DPB) 230, the inter prediction unit 344 and the intra prediction unit 354 are also referred to as forming the “built-in decoder” of video encoder 20. Accordingly, the inverse quantization unit 310 may be identical in function to the inverse quantization unit 110, the inverse transform processing unit 312 may be identical in function to the inverse transform processing unit 212, the reconstruction unit 314 may be identical in function to reconstruction unit 214, the loop filter 320 may be identical in function to the loop filter 220, and the decoded picture buffer 330 may be identical in function to the decoded picture buffer 230. Therefore, the explanations provided for the respective units and functions of the video 20 encoder apply correspondingly to the respective units and functions of the video decoder 30.

Entropy Decoding

The entropy decoding unit 304 is configured to parse the bitstream 21 (or in general encoded picture data 21) and perform, for example, entropy decoding to the encoded picture data 21 to obtain, e.g., quantized coefficients 309 and/or decoded coding parameters (not shown in FIG. 3), e.g. any or all of inter prediction parameters (e.g. reference picture index and motion vector), intra prediction parameter (e.g. intra prediction mode or index), transform parameters, quantization parameters, loop filter parameters, and/or other syntax elements. Entropy decoding unit 304 may be configured to apply the decoding algorithms or schemes corresponding to the encoding schemes as described with regard to the entropy encoding unit 270 of the encoder 20. Entropy decoding unit 304 may be further configured to provide inter prediction parameters, intra prediction parameter and/or other syntax elements to the mode application unit 360 and other parameters to other units of the decoder 30. Video decoder 30 may receive the syntax elements at the video slice level and/or the video block level. In addition or as an alternative to slices and respective syntax elements, tile groups and/or tiles and respective syntax elements may be received and/or used.

Inverse Quantization

The inverse quantization unit 310 may be configured to receive quantization parameters (QP) (or in general information related to the inverse quantization) and quantized coefficients from the encoded picture data 21 (e.g. by parsing and/or decoding, e.g. by entropy decoding unit 304) and to apply based on the quantization parameters an inverse quantization on the decoded quantized coefficients 309 to obtain dequantized coefficients 311, which may also be referred to as transform coefficients 311. The inverse quantization process may include use of a quantization parameter determined by video encoder 20 for each video block in the video slice (or tile or tile group) to determine a degree of quantization and, likewise, a degree of inverse quantization that should be applied.

Inverse Transform

Inverse transform processing unit 312 may be configured to receive dequantized coefficients 311, also referred to as transform coefficients 311, and to apply a transform to the dequantized coefficients 311 in order to obtain reconstructed residual blocks 213 in the sample domain. The reconstructed residual blocks 213 may also be referred to as transform blocks 313. The transform may be an inverse transform, e.g., an inverse DCT, an inverse DST, an inverse integer transform, or a conceptually similar inverse transform process. The inverse transform processing unit 312 may be further configured to receive transform parameters or corresponding information from the encoded picture data 21 (e.g. by parsing and/or decoding, e.g. by entropy decoding unit 304) to determine the transform to be applied to the dequantized coefficients 311.

Reconstruction

The reconstruction unit 314 (e.g. adder or summer 314) may be configured to add the reconstructed residual block 313, to the prediction block 365 to obtain a reconstructed block 315 in the sample domain, e.g. by adding the sample values of the reconstructed residual block 313 and the sample values of the prediction block 365.

Filtering

The loop filter unit 320 (either in the coding loop or after the coding loop) is configured to filter the reconstructed block 315 to obtain a filtered block 321, e.g. to smooth pixel transitions, or otherwise improve the video quality. The loop filter unit 320 may comprise one or more loop filters such as a de-blocking filter, a sample-adaptive offset (SAO) filter or one or more other filters, e.g. a bilateral filter, an adaptive loop filter (ALF), a sharpening, a smoothing filters or a collaborative filters, or any combination thereof. Although the loop filter unit 320 is shown in FIG. 3 as being an in loop filter, in other configurations, the loop filter unit 320 may be implemented as a post loop filter.

Decoded Picture Buffer

The decoded video blocks 321 of a picture are then stored in decoded picture buffer 330, which stores the decoded pictures 331 as reference pictures for subsequent motion compensation for other pictures and/or for output respectively display.

The decoder 30 is configured to output the decoded picture 311, e.g. via output 312, for presentation or viewing to a user.

Prediction

The inter prediction unit 344 may be identical to the inter prediction unit 244 (in particular to the motion compensation unit) and the intra prediction unit 354 may be identical to the inter prediction unit 254 in function, and performs split or partitioning decisions and prediction based on the partitioning and/or prediction parameters or respective information received from the encoded picture data 21 (e.g. by parsing and/or decoding, e.g. by entropy decoding unit 304). Mode application unit 360 may be configured to perform the prediction (intra or inter prediction) per block based on reconstructed pictures, blocks or respective samples (filtered or unfiltered) to obtain the prediction block 365.

When the video slice is coded as an intra coded (I) slice, intra prediction unit 354 of mode application unit 360 is configured to generate prediction block 365 for a picture block of the current video slice based on a signaled intra prediction mode and data from previously decoded blocks of the current picture. When the video picture is coded as an inter coded (i.e., B, or P) slice, inter prediction unit 344 (e.g. motion compensation unit) of mode application unit 360 is configured to produce prediction blocks 365 for a video block of the current video slice based on the motion vectors and other syntax elements received from entropy decoding unit 304. For inter prediction, the prediction blocks may be produced from one of the reference pictures within one of the reference picture lists. Video decoder 30 may construct the reference frame lists, List 0 and List 1, using default construction techniques based on reference pictures stored in DPB 330. The same or similar may be applied for or by embodiments using tile groups (e.g. video tile groups) and/or tiles (e.g. video tiles) in addition or alternatively to slices (e.g. video slices), e.g. a video may be coded using I, P or B tile groups and/or tiles.

Mode application unit 360 is configured to determine the prediction information for a video block of the current video slice by parsing the motion vectors or related information and other syntax elements, and uses the prediction information to produce the prediction blocks for the current video block being decoded. For example, the mode application unit 360 uses some of the received syntax elements to determine a prediction mode (e.g., intra or inter prediction) used to code the video blocks of the video slice, an inter prediction slice type (e.g., B slice, P slice, or GPB slice), construction information for one or more of the reference picture lists for the slice, motion vectors for each inter encoded video block of the slice, inter prediction status for each inter coded video block of the slice, and other information to decode the video blocks in the current video slice. The same or similar may be applied for or by embodiments using tile groups (e.g. video tile groups) and/or tiles (e.g. video tiles) in addition or alternatively to slices (e.g. video slices), e.g. a video may be coded using I, P or B tile groups and/or tiles.

Embodiments of the video decoder 30 as shown in FIG. 3 may be configured to partition and/or decode the picture by using slices (also referred to as video slices), wherein a picture may be partitioned into or decoded using one or more slices (typically non-overlapping), and each slice may comprise one or more blocks (e.g. CTUs).

Embodiments of the video decoder 30 as shown in FIG. 3 may be configured to partition and/or decode the picture by using tile groups (also referred to as video tile groups) and/or tiles (also referred to as video tiles), wherein a picture may be partitioned into or decoded using one or more tile groups (typically non-overlapping), and each tile group may comprise, e.g. one or more blocks (e.g. CTUs) or one or more tiles, wherein each tile, e.g. may be of rectangular shape and may comprise one or more blocks (e.g. CTUs), e.g. complete or fractional blocks.

Other variations of the video decoder 30 can be used to decode the encoded picture data 21. For example, the decoder 30 can produce the output video stream without the loop filtering unit 320. For example, a non-transform based decoder 30 can inverse-quantize the residual signal directly without the inverse-transform processing unit 312 for certain blocks or frames. In another implementation, the video decoder 30 can have the inverse-quantization unit 310 and the inverse-transform processing unit 312 combined into a single unit.

It should be understood that, in the encoder 20 and the decoder 30, a processing result of a current step may be further processed and then output to the next step. For example, after interpolation filtering, motion vector derivation or loop filtering, a further operation, such as Clip or shift, may be performed on the processing result of the interpolation filtering, motion vector derivation or loop filtering.

It should be noted that further operations may be applied to the derived motion vectors of current block (including but not limit to control point motion vectors of affine mode, sub-block motion vectors in affine, planar, ATMVP modes, temporal motion vectors, and so on). For example, the value of motion vector is constrained to a predefined range according to its representing bit. If the representing bit of motion vector is bitDepth, then the range is −2{circumflex over ( )}(bitDepth−1)˜2{circumflex over ( )}(bitDepth−1)−1, where “{circumflex over ( )}” means exponentiation. For example, if bitDepth is set equal to 16, the range is −32768˜32767; if bitDepth is set equal to 18, the range is −131072˜131071. For example, the value of the derived motion vector (e.g. the MVs of four 4×4 sub-blocks within one 8×8 block) is constrained such that the max difference between integer parts of the four 4×4 sub-block MVs is no more than N pixels, such as no more than 1 pixel. Here provides two methods for constraining the motion vector according to the bitDepth.

Method 1: remove the overflow MSB (most significant bit) by flowing operations

ux=(mvx+2^(bitDepth))%2^(bitDepth)  (1)

mvx=(ux>=2^(bitDepth)−1)?(ux−2^(bitDepth)):ux  (2)

uy=(mvy+2^(bitDepth))%2^(bitDepth)  (3)

mvy=(uy>=2^(bitDepth−1))?(uy−2^(bitDepth)):uy  (4)

where mvx is a horizontal component of a motion vector of an image block or a sub-block, mvy is a vertical component of a motion vector of an image block or a sub-block, and ux and uy indicates an intermediate value;

For example, if the value of mvx is −32769, after applying formula (1) and (2), the resulting value is 32767. In computer system, decimal numbers are stored as two's complement. The two's complement of −32769 is 1,0111,1111,1111,1111 (17 bits), then the MSB is discarded, so the resulting two's complement is 0111,1111,1111,1111 (decimal number is 32767), which is same as the output by applying formula (1) and (2).

ux=(mvpx+mvdx+2^(bitDepth))%2^(bitDepth)  (5)

mvx=(ux>=2^(bitDepth−1))?(ux−2^(bitDepth)):ux  (6)

uy=(mvpy+mvdy+2^(bitDepth))%2^(bitDepth)  (7)

mvy=(uy>=2^(bitDepth)-1)?(uy−2^(bitDepth)):uy  (8)

The operations may be applied during the sum of mvp and mvd, as shown in formula (5) to (8).

Method 2: remove the overflow MSB by clipping the value

vx=Clip3(−2^(bitDepth−1),2^(bitDepth−1)−1,vx)

vy=Clip3(−2^(bitDepth−1),2^(bitDepth−1)−1,vy)

where vx is a horizontal component of a motion vector of an image block or a sub-block, vy is a vertical component of a motion vector of an image block or a sub-block; x, y and z respectively correspond to three input value of the MV clipping process, and the definition of function Clip3 is as follow:

${Clip3\left( {x,y,z} \right)} = \left\{ \begin{matrix} x & ; & {z < x} \\ y & ; & {z > y} \\ z & ; & {otherwise} \end{matrix} \right.$

FIG. 4 is a schematic diagram of a video coding device 400 according to an embodiment of the disclosure. The video coding device 400 is suitable for implementing the disclosed embodiments as described herein. In an embodiment, the video coding device 400 may be a decoder such as video decoder 30 of FIG. 1A or an encoder such as video encoder 20 of FIG. 1A.

The video coding device 400 comprises ingress ports 410 (or input ports 410) and receiver units (Rx) 420 for receiving data; a processor, logic unit, or central processing unit (CPU) 430 to process the data; transmitter units (Tx) 440 and egress ports 450 (or output ports 450) for transmitting the data; and a memory 460 for storing the data. The video coding device 400 may also comprise optical-to-electrical (OE) components and electrical-to-optical (EO) components coupled to the ingress ports 410, the receiver units 420, the transmitter units 440, and the egress ports 450 for egress or ingress of optical or electrical signals.

The processor 430 is implemented by hardware and software. The processor 430 may be implemented as one or more CPU chips, cores (e.g., as a multi-core processor), FPGAs, ASICs, and DSPs. The processor 430 is in communication with the ingress ports 410, receiver units 420, transmitter units 440, egress ports 450, and memory 460. The processor 430 comprises a coding module 470. The coding module 470 implements the disclosed embodiments described above. For instance, the coding module 470 implements, processes, prepares, or provides the various coding operations. The inclusion of the coding module 470 therefore provides a substantial improvement to the functionality of the video coding device 400 and effects a transformation of the video coding device 400 to a different state. Alternatively, the coding module 470 is implemented as instructions stored in the memory 460 and executed by the processor 430.

The memory 460 may comprise one or more disks, tape drives, and solid-state drives and may be used as an over-flow data storage device, to store programs when such programs are selected for execution, and to store instructions and data that are read during program execution. The memory 460 may be, for example, volatile and/or non-volatile and may be a read-only memory (ROM), random access memory (RAM), ternary content-addressable memory (TCAM), and/or static random-access memory (SRAM).

FIG. 5 is a simplified block diagram of an apparatus 500 that may be used as either or both of the source device 12 and the destination device 14 from FIG. 1 according to an exemplary embodiment.

A processor 502 in the apparatus 500 can be a central processing unit. Alternatively, the processor 502 can be any other type of device, or multiple devices, capable of manipulating or processing information now-existing or hereafter developed. Although the disclosed implementations can be practiced with a single processor as shown, e.g., the processor 502, advantages in speed and efficiency can be achieved using more than one processor.

A memory 504 in the apparatus 500 can be a read only memory (ROM) device or a random access memory (RAM) device in an implementation. Any other suitable type of storage device can be used as the memory 504. The memory 504 can include code and data 506 that is accessed by the processor 502 using a bus 512. The memory 504 can further include an operating system 508 and application programs 510, the application programs 510 including at least one program that permits the processor 502 to perform the methods described here. For example, the application programs 510 can include applications 1 through N, which further include a video coding application that performs the methods described here.

The apparatus 500 can also include one or more output devices, such as a display 518. The display 518 may be, in one example, a touch sensitive display that combines a display with a touch sensitive element that is operable to sense touch inputs. The display 518 can be coupled to the processor 502 via the bus 512.

Although depicted here as a single bus, the bus 512 of the apparatus 500 can be composed of multiple buses. Further, the secondary storage 514 can be directly coupled to the other components of the apparatus 500 or can be accessed via a network and can comprise a single integrated unit such as a memory card or multiple units such as multiple memory cards. The apparatus 500 can thus be implemented in a wide variety of configurations.

In VVC Draft 4.0 (JVET-M1001), transform cores DST-VII (DST 7), DCT-VIII (DCT 8) and DCT-II (DCT 2) are disclosed for the transform process.

In addition to DCT-II which has been employed in HEVC, a Multiple Transform Selection (MTS) scheme is used for residual coding for both inter and intra coded blocks. Multiple selected transforms DCT8 or DST7 are used in the MTS scheme. Compared with HEVC, DST-VII and DCT-VIII are newly introduced transform cores. Table 1 shows the basic functions of the selected transform core. Normally, a transform core comprises a set of coefficients that are used for a transform process. A transform core may be indicated by formulization, or a transform core may be indicated by a table or a matrix which comprises the mathematical rounded coefficients from the mathematically defined function. The rounding is aiming to simplify the hardware design (for example, after rounding, a smaller size (e.g. 4×4) transform core can directly downsample from a larger size transform core (e.g. 16×16)). After rounding, the coefficients still obey the mathematical deification of a transform.

TABLE 1 Transform basis functions of DCT-II/VIII and DST-VII for N-point input Transform core Basis function T_(i)(j), i, j = 0, 1, . . . , N − 1 DCT-II ${T_{i}(j)} = {\omega_{0} \cdot \sqrt{\frac{2}{N}} \cdot {\cos\left( \frac{\pi \cdot i \cdot \left( {{2\; j} + 1} \right)}{2\; N} \right)}}$ ${where},{\omega_{0} = \left\{ {{\begin{matrix} \sqrt{\frac{2}{N}} & {i = 0} \\ 1 & {i \neq 0} \end{matrix}\omega_{0}} = \left\{ \begin{matrix} \sqrt{\frac{2}{N}} & {i = 0} \\ 1 & {i \neq 0} \end{matrix} \right.} \right.}$ DCT-VIII ${T_{i}(j)} = {\sqrt{\frac{4}{{2\; N} + 1}} \cdot {\cos\left( \frac{\pi \cdot \left( {{2\; i} + 1} \right) \cdot \left( {{2\; j} + 1} \right)}{{4\; N} + 2} \right)}}$ DST-VII ${T_{i}(j)} = {\sqrt{\frac{4}{{2\; N} + 1}} \cdot {\sin\left( \frac{\pi \cdot \left( {{2\; i} + 1} \right) \cdot \left( {j + 1} \right)}{{2\; N} + 1} \right)}}$

In another example, these transform cores are indicated by a transform matrix. In these examples, a variable nTbS specifying the transform block size or the horizontal sample size of scaled transform coefficients.

DST-VII:

-   -   if nTbs is equal to 4, the following applies:

$\begin{matrix} {{{{{transMatrix}\lbrack m\rbrack}\lbrack n\rbrack} = \left\{ {\begin{Bmatrix} 29 & 55 & 74 & 84 \end{Bmatrix}\begin{Bmatrix} 74 & 74 & 0 & {- 74} \end{Bmatrix}\begin{Bmatrix} 84 & {- 29} & {- 74} & 55 \end{Bmatrix}\begin{Bmatrix} 55 & {- 84} & 74 & {- 29} \end{Bmatrix}} \right\}},} & (1206) \end{matrix}$

-   -   Otherwise, if nTbs is equal to 8, the following applies:

$\begin{matrix} {{{{{transMatrix}\lbrack m\rbrack}\lbrack n\rbrack} = \left\{ {\begin{Bmatrix} 17 & 32 & 46 & 60 & 71 & 78 & 85 & 86 \end{Bmatrix}\begin{Bmatrix} 46 & 78 & 86 & 71 & 32 & {- 17} & {- 60} & {- 85} \end{Bmatrix}\begin{Bmatrix} 71 & 85 & 32 & {- 46} & {- 86} & {- 60} & 17 & 78 \end{Bmatrix}\begin{Bmatrix} 85 & 46 & {- 60} & {- 78} & 17 & 86 & 32 & {- 71} \end{Bmatrix}\begin{Bmatrix} 86 & {- 17} & {- 85} & 32 & 78 & {- 46} & {- 71} & 60 \end{Bmatrix}\begin{Bmatrix} 78 & {- 71} & {- 17} & 85 & {- 60} & {- 32} & 86 & {- 46} \end{Bmatrix}\begin{Bmatrix} 60 & {- 86} & 71 & {- 17} & {- 46} & 85 & {- 78} & 32 \end{Bmatrix}\begin{Bmatrix} 32 & {- 60} & 78 & {- 86} & 85 & {- 71} & 46 & {- 17} \end{Bmatrix}} \right\}},} & (1207) \end{matrix}$

-   -   Otherwise, if nTbs is equal to 16, the following applies:

$\begin{matrix} {{{{{transMatrix}\lbrack\ m\rbrack}\lbrack n\rbrack} = \left\{ {\begin{Bmatrix} 8 & 17 & 25 & 33 & 40 & 48 & 55 & 62 & 68 & 73 & 77 & 81 & 85 & 87 & 88 & 88 \end{Bmatrix}\begin{Bmatrix} 25 & 48 & 68 & 81 & 88 & 88 & 81 & 68 & 48 & 25 & 0 & {- 25} & {- 48} & {- 68} & {- 81} & {- 88} \end{Bmatrix}\begin{Bmatrix} 40 & 73 & 88 & 85 & 62 & 25 & {- 17} & {- 55} & {- 81} & {- 88} & {- 77} & {- 48} & {- 8} & 33 & 68 & 87 \end{Bmatrix}\begin{Bmatrix} 55 & 87 & 81 & 40 & {- 17} & {- 68} & {- 88} & {- 73} & {- 25} & 33 & 77 & 88 & 62 & 8 & {- 48} & {- 85} \end{Bmatrix}\begin{Bmatrix} 68 & 88 & 48 & {- 25} & {- 81} & {- 81} & {- 25} & 48 & 88 & 68 & 0 & {- 68} & {- 88} & {- 48} & 25 & 81 \end{Bmatrix}\begin{Bmatrix} 77 & 77 & 0 & {- 77} & {- 77} & 0 & 77 & 77 & 0 & {- 77} & {- 77} & 0 & 77 & 77 & 0 & {- 77} \end{Bmatrix}\begin{Bmatrix} 85 & 55 & {- 48} & {- 87} & {- 8} & 81 & 62 & {- 40} & {- 88} & {- 17} & 77 & 68 & {- 33} & {- 88} & {- 25} & 73 \end{Bmatrix}\begin{Bmatrix} 88 & 25 & {- 81} & {- 48} & 68 & 68 & {- 48} & {- 81} & 25 & 88 & 0 & {- 88} & {- 25} & 81 & 48 & {- 68} \end{Bmatrix}\begin{Bmatrix} 88 & {- 8} & {- 88} & 17 & 87 & {- 25} & {- 85} & 33 & 81 & {- 40} & {- 77} & 48 & 73 & {- 55} & {- 68} & 62 \end{Bmatrix}\begin{Bmatrix} 87 & {- 40} & {- 68} & 73 & 33 & {- 88} & 8 & 85 & {- 48} & {- 62} & 77 & 25 & {- 88} & 17 & 81 & {- 55} \end{Bmatrix}\begin{Bmatrix} 81 & {- 68} & {- 25} & 88 & {- 48} & {- 48} & 88 & {- 25} & {- 68} & 81 & 0 & {- 81} & 68 & 25 & {- 88} & 48 \end{Bmatrix}\begin{Bmatrix} 73 & {- 85} & 25 & 55 & {- 88} & 48 & 33 & {- 87} & 68 & 8 & {- 77} & 81 & {- 17} & {- 62} & 88 & {- 40} \end{Bmatrix}\begin{Bmatrix} 62 & {- 88} & 68 & {- 8} & {- 55} & 88 & {- 73} & 17 & 48 & {- 87} & 77 & {- 25} & {- 40} & 85 & {- 81} & 33 \end{Bmatrix}\begin{Bmatrix} 48 & {- 81} & 88 & {- 68} & 25 & 25 & {- 68} & 88 & {- 81} & 48 & 0 & {- 48} & 81 & {- 88} & 68 & {- 25} \end{Bmatrix}\begin{Bmatrix} 33 & {- 62} & 81 & {- 88} & 85 & {- 68} & 40 & {- 8} & {- 25} & 55 & {- 77} & 88 & {- 87} & 73 & {- 48} & 17 \end{Bmatrix}\begin{Bmatrix} 17 & {- 33} & 48 & {- 62} & 73 & {- 81} & 87 & {- 88} & 88 & {- 85} & 77 & {- 68} & 55 & {- 40} & 25 & {- 8} \end{Bmatrix}} \right\}},} & (1208) \end{matrix}$

-   -   Otherwise, if nTbs is equal to 32, the following applies:         where nTbs is the transform block size. Since the VVC only         supports maximal 32 point DST-VII, the maximal matrix is         32×32.DCT-II:

In order to keep the orthogonality of the transform matrix, these transform matrices are quantized more accurately than the transform matrices in HEVC. In some examples, for keeping the intermediate values of the transformed coefficients within the 16-bit range, after horizontal transform and after the vertical transform, all the coefficients are to have 10-bit.

In order to signal the MTS scheme, separate enabling flags are specified at the SPS level for intra or inter, respectively. When an MTS scheme is enabled at the SPS level, a CU level flag is signaled in a bitstream, and a value of the CU level flag is used to indicate whether MTS is applied to a current CU or not. In an example, MTS is applied only for luma samples. In an example, the CU level flag is signaled when the following conditions are satisfied:

Both the width of the current CU and the height of the current CU are smaller than or equal to 32, and a value of coded block flag CBF flag of the current CU is equal to one.

If a value of the CU level flag is equal to zero, then DCT2 is applied in the horizontal direction of the current CU and the vertical direction of the current CU. If a value of the CU level flag is equal to one, then two additional flags are signaled to indicate the transform type for the horizontal direction and vertical direction, respectively. A mapping relationship for transform type and flag value as shown in the below Table 2. In some examples, 8-bit primary transform cores are used. In an example, the transform cores are the same as the transform cores used in HEVC. In an example, these transform cores comprise 4-point DCT-2 and DST-7, 8-point, 16-point and 32-point DCT-2. Also, other transform cores comprise 64-point DCT-2, 4-point DCT-8, 8-point, 16-point, 32-point DST-7 and DCT-8, use 8-bit primary transform cores.

TABLE 2 Transform and signaling mapping table Intra/inter MTS_CU_flag MTS_Hor_flag MTS_Ver_flag Horizontal Vertical 0 DCT2 1 0 0 DST7 DST7 0 1 DCT8 DST7 1 0 DST7 DCT8 1 1 DCT8 DCT8

As in HEVC, the residual of a block can be coded with a transform skip mode. To avoid the redundancy of syntax coding, a transform skip flag is not signaled when a value of the CU level flag MTS_CU_flag is not equal to zero. Transform skip mode is enabled when both block width and block height are equal to or less than 4.

Intra sub-partition (ISP) coding mode is a tool adopted in VVC Draft 4.0 (JVET-M1001). When the ISP coding mode is applied, the luma intra-predicted block vertically or horizontally is divided into 2 or 4 sub-partitions, depending on the block size dimensions, as shown in Table 3. FIG. 6 and FIG. 7 show examples of the two possibilities. Each sub-partition comprises at least 16 samples.

TABLE 3 Number of sub-partitions depending on the block size Block Size Number of Sub-Partitions 4 × 4 Not divided 4 × 8 and 8 × 4 2 other cases 4

When the intra sub-partition coding mode is enabled for the current block (regardless of the MTS is enabled or disabled for the current block), the transform core is not selected according to an MTS index, rather the transform core is selected based on the intra mode of the current block. In an example, as showed in the following Table 4, trTypeHor indicates a transform core for the horizontal direction of a current block with ISP mode, and trTypeVer indicates a transform core for the vertical direction of the current block with ISP mode.

According to table 4, when a value of trTypeVer is equal to 0 or a value of trTypeHor is equal to 0, transform core DCT2 is selected for the current block; when a value of the trTypeVer is equal to 1 or a value of the trTypeHor is equal to 1, transform core DST7 is selected for the current block.

TABLE 4 Specification of trTypeHor and trTypeVer depending on predModeIntra predModelntra (intra prediction mode for a block) trTypeHor trTypeVer INTRA_PLANAR, ( nTbW (width of the ( nTbH (height of the INTRA_ANGULAR31, transform block) >= 4 transform block) >= 4 INTRA_ANGULAR32, && && INTRA_ANGULAR34, nTbW <= 16) ? 1: 0 nTbH 16) ? 1: 0 INTRA_ANGULAR36, INTRA_ANGULAR37 INTRA_ANGULAR33, 0 0 INTRA_ANGULAR35 INTRA_ANGULAR2, (nTbW >= 4 && 0 INTRA_ANGULAR4,..., INTRA_ANGULAR28, nTbW <= 16) ? 1: 0 INTRA_ANGULAR30, INTRA_ANGULAR39, INTRA_ANGULAR41,..., INTRA_ANGULAR63, INTRA_ANGULAR65 INTRA_ANGULAR3, 0 (nTbH >= 4 && INTRA_ANGULAR5,..., INTRA_ANGULAR27, nTbH <=16) ? 1: 0 INTRA_ANGULAR29, INTRA_ANGULAR38, INTRA_ANGULAR40,..., INTRA_ANGULAR64, INTRA_ANGULAR66

An intra shape adaptive implicit transform core selection is disclosed by JVET-M0303.

In the intra shape adaptive implicit transform core selection method, it is proposed to use DST7 for a shorter side of a transform block, and to use DCT2 for a longer side of the transform block. For square blocks, it is proposed to use DST7, if MTS is disabled for a sequence. The shape adaptive is used for intra blocks that are predicted with spatial prediction modes (and disabled for cross-component predicted blocks).

In an example, the intra block transform core selection is performed based on the below equations when MTS is disabled. trTypeHor indicates a transform core for the horizontal direction of a current block with the ISP mode, and trTypeVer indicates a transform core for the vertical direction of the current block with the ISP mode, nTbW is the transform block width, and nTbH is the transform block height.

It is noted that a block is firstly coded with a specific coding mode, and the block is named as a coding block. The coding block may be predicted using a specific prediction method. The difference between the original samples and predicted samples is named as residual signals, and the residual signals are further transformed. The transformed blocks are defined as transform blocks. In normal cases, the coding block sizes (i.e. coding block width, coding block height) are equal to the transform block sizes (i.e. transform block width, transform block height). Following are some example cases where the coding block sizes are not equal to the transform block sizes.

-   -   1. The coding block size is 128×128, it is implicitly split into         4 transform blocks with a size 64×64.     -   2. If the coding block is coded by the ISP mode, the multiple         transform blocks is split from the corresponding coding block.     -   3. If the coding block is coded by the sub-block transform (SBT)         mode, only a portion of the coding block is transformed, so the         transform block size is smaller than the coding block size.

According to the equations, when a value of trTypeVer is equal to 0 or a value of trTypeHor is equal to 0, transform core DCT2 is selected for the current block; when a value of the trTypeVer is equal to 1 or a value of the trTypeHor is equal to 1, transform core DST7 is selected for the current block.

trTypeHor=(nTbW>=4&&nTbW<=16&&nTbW<=nTbH)?1:0  EQ-1

trTypeVer=(nTbH>=4&&nTbH<=16&&nTbH<=nTbW)?1:0  EQ-2

In EQ-1 and EQ-2, nTbW indicates a width of the current transform unit (TU), nTbH indicates a height of the current TU, nSbTbW indicate a width of a sub-TU resulting from the ISP split, and nSbTbH indicate a height of the sub-TU resulting from the ISP split.

Here the size limitation (4 and 16) is used for luma samples. A block could have luma components and chroma components. If a video sequence is not chroma subsampled, then the luma sample size and chroma sample size are equal. If the video sequence is chroma subsampled (for example a 4:2:0 video), then chroma sample size is equal to luma sample size divided by two. Normally, the mentioned threshold is in luma sample size.

In some examples, the implicit transform core selection of ISP is based on intra mode with a complex table. The table also introduced dependency between the transform core selection and intra mode. Additional, the implicit transform core selection of ISP and intra shape adaptive method is not harmonized.

The following proposed solutions are addressing the problems of ISP implicit transform core selection complexity, ISP transform core selection dependency with intra mode, ISP and intra shape adaptive implicit transform core selection harmonization. In some embodiments, these solutions are based on DST7, DCT8 transform cores enabled by a high level flag case (a value of sps_mts_enabled_flag is equal to 1).

In an embodiment,

Solution 1:

According to solution 1, shape adaptive implicit transform core selection is applied depending on an intra block processed by using ISP mode, with block width and height restrictions.

If a current intra block is processed by using ISP mode, the equations EQ-1 and EQ-2 are used to determine the selected transform core of the current block. The utilization of EQ-1 and EQ-2 here is not dependent on whether the MTS mode is enabled or disabled.

For a current intra block which is not processed by using ISP mode, if MTS is enabled in the sequence level, then transform core is selected based on an MTS index. Otherwise (if MTS is disabled in the sequence level), the transform core is selected based on EQ-1 and EQ-2.

This proposed solution harmonizes the ISP and intra shape adaptive implicit transform core selection. Furthermore, the proposed solution reduced the ISP mode implicit transform core selection complexity, and removed the intra mode dependency without change of the worst case.

In an example, as the calculation of DST 7 is more complex than the calculation of DCT 2, the worst case is that all ISP blocks use DST7 for both horizontal and vertical transform cores. The proposed method does not change the worst case of ISP implicit transform core selection.

In another embodiment,

Solution 2:

According to solution 2, shape adaptive implicit transform core selection is applied, depending on an intra block processed by using ISP mode with sub-block width and height restrictions. The sub-block results from the ISP split.

If a current Intra block is processed by using ISP mode, equations EQ-3 and EQ-4 are used to determine the transform core for a current block. The utilization of EQ-3 and EQ-4 here does not depend on whether the MTS mode is enabled or disabled. In EQ-3 and EQ-4, nTbW indicates a width of the current TU, nTbH indicates a height of the current TU, nSbTbW indicates a width of the sub-TU resulting from ISP split, and nSbTbH indicates a height of the sub-TU resulting from ISP split.

trTypeHor=(nTbW>=4&&nTbW<=16&&nSbTbW<=nSbTbH)?1:0  EQ-3

trTypeVer=(nTbH>=4&&nTbH<=16&&nSbTbH<=nSbTbW)?1:0  EQ-4

For a current intra block which is not processed by using ISP mode, if MTS is enabled in the sequence level, transform core is selected based on a MTS index. If MTS is disabled in the sequence level, transform core is selected based on EQ-1 and EQ-2.

This proposed solution harmonizes the ISP and intra shape adaptive implicit transform core selection. Furthermore the proposed solution reduced the ISP mode implicit transform core selection complexity, and removed the intra mode dependency without change of the worst case.

In an example, because the calculation of DST7 is more complex than the calculation of DCT 2, the worst case is that all ISP blocks use DST7 for both horizontal and vertical transform core. The proposed method does not change the worst case of ISP implicit transform core selection.

In another embodiment,

Solution 3

According to solution 3, it is proposed to use transform core DST7 for an intra block which is processed by using ISP mode with size restriction.

If a current intra block is processed by using ISP mode, the equations EQ-5 and EQ-6 are used to determine the transform core of the current block. The utilization of EQ-5 and EQ-6 here does not depend on whether the MTS mode is enabled or disabled.

trTypeHor=(nTbW>=4&&nTbW<=16)?1:0  EQ-5

trTypeVer=(nTbH>=4&&nTbH<=16)?1:0  EQ-6

In an example, if the TU width is larger than or equal to 4 in luma samples, and the TU width is smaller than or equal to 16 samples, then DST7 is used for the horizontal direction. Otherwise, DCT2 is used for the horizontal direction. In an example, a picture of a video has luma component (Y) and chroma components (Cb,Cr). If the chroma is subsampled (for example 4:2:0 video), 4 luma samples correspond to 2 chroma samples.

In an example, if the TU height is larger than or equal to 4 in luma samples, and the TU height is smaller than or equal to 16 in luma samples, then DST7 is used for the vertical direction. Otherwise, DCT2 is used for the vertical direction.

For a current intra block which is not processed by using ISP mode, if MTS is enabled in the sequence level, then transform core is selected based on an MTS index. If MTS is disabled in the sequence level, transform core is selected based on EQ-1 and EQ-2.

This proposed solution reduces the ISP mode implicit transform core selection complexity and removes the intra mode dependency without change of the worst case.

In an example, as the calculation of DST7 is more complex than the calculation of DCT 2, the worst case is that all ISP blocks use DST7 for both horizontal and vertical transform core. The proposed method does not change the worst case of ISP implicit transform core selection.

In another embodiment, Solution 4:

According to solution 4, shape adaptive implicit transform core selection is applied depending on the TU width and height for intra block processed by using the ISP mode, when the intra prediction of the block does not use the planar mode. If the block is predicted using the planar intra prediction mode, then both horizontal and vertical transform cores use DST 7 with size restrictions.

In an example, if a current intra block is processed by using ISP mode, equations EQ-1 and EQ-2 are used to determine the transform core of the current block, when an intra prediction mode of the current intra block is not the planar mode. The utilization of EQ-1 and EQ-2 does not depend on whether MTS mode is enabled or disabled.

In an example, if the current intra block is processed by using ISP mode, equations EQ-5 and EQ-6 are used to determine the transform core of the current block, when an intra prediction mode of the current intra block is the planar mode. The utilization of EQ-5 and EQ-6 here does not depend on whether the MTS mode is enabled or disabled.

For a current intra block which is not processed by using ISP mode, if MTS is enabled in the sequence level, transform core is selected based on an MTS index. If MTS is disabled in the sequence level, transform core is selected based on EQ-1 and EQ-2.

This proposed solution harmonizes the ISP and intra shape adaptive implicit transform core selection. Furthermore, the solution reduces the ISP mode implicit transform core selection complexity without change of the worst case.

In an example, as the calculation of DST7 is more complex than the calculation of DCT 2, the worst case is that all ISP blocks use DST7 for both horizontal and vertical transform core. The proposed method does not change the worst case of ISP implicit transform core selection.

In another embodiment,

Solution 5:

According to solution 5, it is proposed to select a transform core based on the ISP split direction.

In an example, if a current Intra block is processed by using ISP mode, equations EQ-7 and EQ-8 are used to determine the transform core of current block, when an intra prediction mode of the current intra block is not the planar mode. The utilization of EQ-7 and EQ-8 here does not depend on whether the MTS mode is enabled or disabled.

trTypeHor=(nTbW>=4&&nTbW<=16&&IntraSubPartitionsSplitType==ISP_VER_SPLIT)?1:0  EQ-7

trTypeVer=(nTbH>=4&&nTbH<=16&&IntraSubPartitionsSplitType==ISP_HOR_SPLIT)?1:0  EQ-8

IntraSubPartitionsSplitType is used to indicate a type of ISP mode. In some examples, ISP mode may comprise: split into 4 subTU, split into 2 subTU, horizontal, vertical or not split types.

ISP_VER_SPLIT is used to indicate Vertically ISP split mode; ISP_HOR_SPLIT is used to indicate horizontal ISP split mode.

When the current intra block is using vertical ISP split, block width is larger than or equal to 4 in luma samples and the block height is smaller than or equal to 16 in luma samples, then DST7 is selected for the horizontal transform core (transform core used for horizontal direction). Otherwise, DCT2 is selected for the horizontal transform core.

In an example, if the current intra block uses horizontal ISP split, block height is larger than or equal to 4 in luma samples, and the block height is smaller than or equal to 16 in luma samples, then DST7 is selected for the vertical transform core (transform core used for vertical direction). Otherwise, DCT2 is selected for the vertical transform core.

For a current intra block which is not processed by using ISP mode, if MTS is enabled in the sequence level, transform core is selected based on an MTS index. If MTS is disabled in the sequence level, the transform core is selected based on EQ-1 and EQ-2.

This proposed solution reduced the ISP mode implicit transform core selection complexity and removed the intra mode dependency without change of the worst case.

In an example, because the calculation of DST7 is more complex than the calculation of DCT 2, the worst case of prior art is that all ISP blocks use DST7 for both horizontal and vertical transform core. The proposed method does not change the worst case of ISP implicit transform core selection.

In another embodiment,

Solution 6

According to the solution 6, it is proposed to use only DST7 cores for intra block, when MTS is disabled in sequence level for both inter and intra slice.

In an example, if MTS is disabled in the sequence level for both inter and intra slice, DST7 is used for horizontal direction when the width of the current intra block is larger than or equal to 4 samples and smaller than or equal to 16 samples, otherwise DCT2 is selected as shown in EQ-9.

In an example, if MTS is disabled in the sequence level for both inter and intra slice, DST7 is used for vertical direction when the height of the current intra block is larger than or equal to 4 samples and smaller than or equal to 16 samples, otherwise DCT2 is selected as descripted in EQ-10.

trTypeHor=(nTbW>=4&&nTbW<=16)?1:0  EQ-9

trTypeVer=(nTbH>=4&&nTbH<=16)?1:0  EQ-10

In one embodiment, the proposed solution 6 is harmonized with solution 3, and solution 6 brings additional coding gain without additional complexity.

In another embodiment,

Solution 7

According to the solution 7, it is proposed to use the shape and ratio adaptive method to select the transform core for an intra block, when MTS is disabled in sequence level for both inter and intra slice.

In an example, if MTS is disabled in the sequence level for both inter and intra slice, for an intra block with both height and width larger than or equal to 4 in luma samples and smaller than or equal to 16 in luma samples (for example, nTbW<=16 && nTbW>=4 && nTbH<=16 && nTbH>=4), if a value of the ratio of block width and height (calculated in EQ-11) of the current block is smaller than or equal to 2, then DST7 is used for both horizontal and vertical directions;

otherwise (a value of the ratio is larger than 2), transform core DST7 is used for the shorter edge, transform core DCT2 is used for the longer edge. For example, if a block with width 16 and height 4, then the shorter edge is 4 and the longer edge is 16. In this example, the transform core DST7 is used for the shorter edge with height 4 (vertical direction), the transform core DCT2 is used for the longer edge with width 16 (horizontal direction).

The method is descripted according to EQ-11 and EQ-12, and the Ratio is calculated according to EQ-13, where log 2( ) is logarithm scaling based 2, and abs( ) is absolute value operator.

trTypeHor=(nTbW>=4&&nTbW<=16&&(nTbW<nTbH∥Ratio<=2))?1:0  EQ-11

trTypeVer=(nTbH>=4&&nTbH<=16&&(nTbH<nTbW∥Ratio<=2))?1:0  EQ-12

Ratio=log 2(abs(width−height))  EQ-13.

In one embodiment, the proposed solution 7 brings additional coding gain without additional complexity.

In another embodiment,

Solution 8

According to solution 8, the ratio of block width and height in solution 7 can be calculated based on EQ-14

Ratio=1<<abs(log 2(width)−log 2(height))  EQ-14.

Where the “<<” is left bit shift operation, log 2( ) is the logarithm scaling based on 2, abs( ) is the absolute value operation.

In other words, the ratio is width/height, if the width is larger than height; otherwise (width is smaller than or equal to height), the ratio is height/width.

Solution 9

According to solution 9, solution 7 or solution 8 can be combined with solution 1, 2 and 4, to replace the shape adaptive part, with solution 7 or solution 8 proposed shape ratio adaptive method.

Example 1. A method of coding implemented by a decoding device or an encoding device, comprising:

when a prediction mode of a current block is intra prediction, and the current block is processed by using Intra sub-partition, ISP, coding mode,

determining whether a width of the current block is larger than or equal to a first threshold (in an example, the first threshold is 4, the unit for the first threshold is luma samples) or not, and whether the width of the current block is smaller than or equal to a second threshold (in an example, the second threshold is 16, the unit for the second threshold is luma samples) or not;

when the width of the current block is larger than or equal to the first threshold and smaller than or equal to the second threshold, a transform core DST 7 is used for horizontal transform of the current block.

Example 2. The method of example 1, wherein when the width of the current block is smaller than the first threshold, or when the width of the current block is larger than the second threshold,

a transform core DCT 2 is used for horizontal transform of the current block.

Example 3. A method of coding implemented by a decoding device or an encoding device, comprising:

when a prediction mode of a current block is intra prediction, and the current block is processed by using Intra sub-partition, ISP, coding mode,

determining whether a height of the current block is larger than or equal to a third threshold (in an example, the third threshold is 4, the unit for the third threshold is luma samples) or not, and whether the height of the current block is smaller than or equal to a fourth threshold (in an example, the fourth threshold is 16, the unit for the fourth threshold is luma samples) or not;

when the height of the current block is larger than or equal to the third threshold and smaller than or equal to the fourth threshold, a transform core DST 7 is used for vertical transform of the current block.

Example 4. The method of example 3, wherein when the height of the current block is smaller than the third threshold, or when the height of the current block is larger than the fourth threshold,

a transform core DCT 2 is used for vertical transform of the current block.

Example 5. A method of coding implemented by a decoding device or an encoding device, comprising:

when a Multiple Transform Selection, MTS, scheme is unavailable for a current block (for example, MTS is turned off in the sequence level for both inter and intra slice),

determining whether a width of the current block is larger than or equal to a first threshold (in an example, the first threshold is 4, the unit for the first threshold is luma samples) or not, and whether the width of the current block is smaller than or equal to a second threshold (in an example, the second threshold is 16, the unit for the second threshold is luma samples) or not;

when the width of the current block is larger than or equal to the first threshold and smaller than or equal to the second threshold, a transform core DST 7 is used for horizontal transform of the current block.

Example 6. The method of example 5, wherein when the width of the current block is smaller than the first threshold, or when the width of the current block is larger than the second threshold,

a transform core DCT 2 is used for horizontal transform of the current block.

Example 7. A method of coding implemented by a decoding device or an encoding device, comprising:

when a Multiple Transform Selection, MTS, scheme is unavailable for a current block (for example, MTS is turned off in the sequence level for both inter and intra slice),

determining whether a height of the current block is larger than or equal to a third threshold (in an example, the third threshold is 4, the unit for the third threshold is luma samples) or not, and whether the height of the current block is smaller than or equal to a fourth threshold (in an example, the fourth threshold is 16, the unit for the fourth threshold is luma samples) or not; when the height of the current block is larger than or equal to the third threshold and smaller than or equal to the fourth threshold, a transform core DST 7 is used for vertical transform of the current block.

Example 8. The method of example 7, wherein when the height of the current block is smaller than the third threshold, or when the height of the current block is larger than the fourth threshold,

a transform core DCT 2 is used for vertical transform of the current block.

Example 9. A method of coding implemented by a decoding device or an encoding device, comprising:

when a Multiple Transform Selection, MTS, scheme is unavailable for a current block (for example, MTS is turned off in the sequence level for both inter and intra slice), a width of the current block is larger than or equal to a first threshold (in an example, the first threshold is 4, the unit for the first threshold is luma samples) and smaller than or equal to a second threshold (in an example, the second threshold is 16, the unit for the second threshold is luma samples), and a height of the current block is larger than or equal to a third threshold (in an example, the third threshold is 4, the unit for the third threshold is luma samples) and smaller than or equal to a fourth threshold (in an example, the fourth threshold is 16, the unit for the fourth threshold is luma samples),

determining whether a value of a ratio of block width and height corresponding to the current block is larger than a fifth threshold (in an example, the fifth threshold is 2) or not,

when the value of the ratio of block width and height is smaller than or equal to the fifth threshold,

a transform core DST 7 is used for horizontal and vertical transform of the current block.

Example 10. The method of example 9, wherein when the value of the ratio of block width and height is larger than the fifth threshold, and the width of the block is smaller than the height of the block,

a transform core DST 7 is used for horizontal transform of the current block and a transform core DCT 2 is used for vertical transform of the current block.

Example 11. The method of example 9 or 10, wherein when the value of the ratio of block width and height is larger than the fifth threshold, and the width of the block is larger than the height of the block,

a transform core DCT 2 is used for horizontal transform of the current block and a transform core DST 7 is used for vertical transform of the current block.

Example 12. An encoder (20) comprising processing circuitry for carrying out the method according to any one of examples 1 to 11.

Example 13. A decoder (30) comprising processing circuitry for carrying out the method according to any one of examples 1 to 11.

Example 14. A computer program product comprising a program code for performing the method according to any one of examples 1 to 11.

Example 15. A decoder or an encoder, comprising:

one or more processors; and

a non-transitory computer-readable storage medium coupled to the processors and storing programming for execution by the processors, wherein the programming, when executed by the processors, configures the decoder to carry out the method according to any one of examples 1 to 11.

Following is an explanation of the applications of the encoding method as well as the decoding method as shown in the above-mentioned embodiments, and a system using them.

FIG. 8 is a block diagram showing a content supply system 3100 for realizing content distribution service. This content supply system 3100 includes capture device 3102, terminal device 3106, and optionally includes display 3126. The capture device 3102 communicates with the terminal device 3106 over communication link 3104. The communication link may include the communication channel 13 described above. The communication link 3104 includes but not limited to WIFI, Ethernet, Cable, wireless (3G/4G/5G), USB, or any kind of combination thereof, or the like.

The capture device 3102 generates data, and may encode the data by the encoding method as shown in the above embodiments. Alternatively, the capture device 3102 may distribute the data to a streaming server (not shown in the Figures), and the server encodes the data and transmits the encoded data to the terminal device 3106. The capture device 3102 includes but not limited to camera, smart phone or Pad, computer or laptop, video conference system, PDA, vehicle mounted device, or a combination of any of them, or the like. For example, the capture device 3102 may include the source device 12 as described above. When the data includes video, the video encoder 20 included in the capture device 3102 may actually perform video encoding processing. When the data includes audio (i.e., voice), an audio encoder included in the capture device 3102 may actually perform audio encoding processing. For some practical scenarios, the capture device 3102 distributes the encoded video and audio data by multiplexing them together. For other practical scenarios, for example in the video conference system, the encoded audio data and the encoded video data are not multiplexed. Capture device 3102 distributes the encoded audio data and the encoded video data to the terminal device 3106 separately.

In the content supply system 3100, the terminal device 310 receives and reproduces the encoded data. The terminal device 3106 could be a device with data receiving and recovering capability, such as smart phone or Pad 3108, computer or laptop 3110, network video recorder (NVR)/digital video recorder (DVR) 3112, TV 3114, set top box (STB) 3116, video conference system 3118, video surveillance system 3120, personal digital assistant (PDA) 3122, vehicle mounted device 3124, or a combination of any of them, or the like capable of decoding the above-mentioned encoded data. For example, the terminal device 3106 may include the destination device 14 as described above. When the encoded data includes video, the video decoder 30 included in the terminal device is prioritized to perform video decoding. When the encoded data includes audio, an audio decoder included in the terminal device is prioritized to perform audio decoding processing.

For a terminal device with its display, for example, smart phone or Pad 3108, computer or laptop 3110, network video recorder (NVR)/digital video recorder (DVR) 3112, TV 3114, personal digital assistant (PDA) 3122, or vehicle mounted device 3124, the terminal device can feed the decoded data to its display. For a terminal device equipped with no display, for example, STB 3116, video conference system 3118, or video surveillance system 3120, an external display 3126 is contacted therein to receive and show the decoded data.

When each device in this system performs encoding or decoding, the picture encoding device or the picture decoding device, as shown in the above-mentioned embodiments, can be used.

FIG. 9 is a diagram showing a structure of an example of the terminal device 3106. After the terminal device 3106 receives stream from the capture device 3102, the protocol proceeding unit 3202 analyzes the transmission protocol of the stream. The protocol includes but not limited to Real Time Streaming Protocol (RTSP), Hyper Text Transfer Protocol (HTTP), HTTP Live streaming protocol (HLS), MPEG-DASH, Real-time Transport protocol (RTP), Real Time Messaging Protocol (RTMP), or any kind of combination thereof, or the like.

After the protocol proceeding unit 3202 processes the stream, stream file is generated. The file is outputted to a demultiplexing unit 3204. The demultiplexing unit 3204 can separate the multiplexed data into the encoded audio data and the encoded video data. As described above, for some practical scenarios, for example in the video conference system, the encoded audio data and the encoded video data are not multiplexed. In this situation, the encoded data is transmitted to video decoder 3206 and audio decoder 3208 without through the demultiplexing unit 3204.

Via the demultiplexing processing, video elementary stream (ES), audio ES, and optionally subtitle are generated. The video decoder 3206, which includes the video decoder 30 as explained in the above mentioned embodiments, decodes the video ES by the decoding method as shown in the above-mentioned embodiments to generate video frame, and feeds this data to the synchronous unit 3212. The audio decoder 3208, decodes the audio ES to generate audio frame, and feeds this data to the synchronous unit 3212. Alternatively, the video frame may store in a buffer (not shown in FIG. 9) before feeding it to the synchronous unit 3212. Similarly, the audio frame may store in a buffer (not shown in FIG. 9) before feeding it to the synchronous unit 3212.

The synchronous unit 3212 synchronizes the video frame and the audio frame, and supplies the video/audio to a video/audio display 3214. For example, the synchronous unit 3212 synchronizes the presentation of the video and audio information. Information may code in the syntax using time stamps concerning the presentation of coded audio and visual data and time stamps concerning the delivery of the data stream itself.

If subtitle is included in the stream, the subtitle decoder 3210 decodes the subtitle, and synchronizes it with the video frame and the audio frame, and supplies the video/audio/subtitle to a video/audio/subtitle display 3216.

Embodiments of the present invention is not limited to the above-mentioned system, and either the picture encoding device or the picture decoding device in the above-mentioned embodiments can be incorporated into other system, for example, a car system.

Mathematical Operators

The mathematical operators used in this application are similar to those used in the C programming language. However, the results of integer division and arithmetic shift operations are defined more precisely, and additional operations are defined, such as exponentiation and real-valued division. Numbering and counting conventions generally begin from 0, e.g., “the first” is equivalent to the 0-th, “the second” is equivalent to the 1-th, etc.

Arithmetic Operators

The following arithmetic operators are defined as follows:

+ Addition − Subtraction (as a two-argument operator) or negation (as a unary prefix operator) * Multiplication, including matrix multiplication x^(y) Exponentiation. Specifies x to the power of y. In other contexts, such notation is used for superscripting not intended for interpretation as exponentiation. / Integer division with truncation of the result toward zero. For example, 7/4 and −7/−4 are truncated to 1 and −7/4 and 7/−4 are truncated to −1. ÷ Used to denote division in mathematical equations where no truncation or rounding is intended. x/y Used to denote division in mathematical equations where no truncation or rounding is intended. $\sum\limits_{i = x}^{y}{f(i)}$ The summation of f(i) with i taking all integer values from x up to and including y. x % y Modulus. Remainder of x divided by y, defined only for integers x and y with x >= 0 and y > 0.

Logical Operators

The following logical operators are defined as follows:

x&&y Boolean logical “and” of x and y x | | y Boolean logical “or” of x and y ! Boolean logical “not” x ? y: z If x is TRUE or not equal to 0, evaluates to the value of y; otherwise, evaluates to the value of z.

Relational Operators

The following relational operators are defined as follows:

> Greater than >= Greater than or equal to < Less than <= Less than or equal to = = Equal to != Not equal to

When a relational operator is applied to a syntax element or variable that has been assigned the value “na” (not applicable), the value “na” is treated as a distinct value for the syntax element or variable. The value “na” is considered not to be equal to any other value.

Bit-Wise Operators

The following bit-wise operators are defined as follows:

& Bit-wise “and”. When operating on integer arguments, operates on a two's complement representation of the integer value. When operating on a binary argument that contains fewer bits than another argument, the shorter argument is extended by adding more significant bits equal to 0. | Bit-wise “or”. When operating on integer arguments, operates on a two's complement representation of the integer value. When operating on a binary argument that contains fewer bits than another argument, the shorter argument is extended by adding more significant bits equal to 0. Bit-wise “exclusive or”. When operating on integer arguments, operates on a two's complement representation of the integer value. When operating on a binary argument that contains fewer bits than another argument, the shorter argument is extended by adding more significant bits equal to 0. x >> y Arithmetic right shift of a two's complement integer representation of x by y binary digits. This function is defined only for non-negative integer values of y. Bits shifted into the most significant bits (MSBs) as a result of the right shift have a value equal to the MSB of x prior to the shift operation. x << y Arithmetic left shift of a two's complement integer representation of x by y binary digits. This function is defined only for non-negative integer values of y. Bits shifted into the least significant bits (LSBs) as a result of the left shift have a value equal to 0.

Assignment Operators

The following arithmetic operators are defined as follows:

= Assignment operator ++ Increment, i.e., x+ +is equivalent to x = x + 1; when used in an array index, evaluates to the value of the variable prior to the increment operation. −− Decrement, i.e., x? ? is equivalent to x = x − 1; when used in an array index, evaluates to the value of the variable prior to the decrement operation. += Increment by amount specified, i.e., x += 3 is equivalent to x = x + 3, and x += (−3) is equivalent to x = x + (−3). −= Decrement by amount specified, i.e., x =3 is equivalent to x = x − 3, and x −= (−3) is equivalent to x = x − (−3).

Range Notation

The following notation is used to specify a range of values:

-   -   x=y . . . z x takes on integer values starting from y to z,         inclusive, with x, y, and z being integer numbers and z being         greater than y.

Mathematical Functions

The following mathematical functions are defined:

${{Abs}(x)} = \left\{ {{\begin{matrix} x & ; & {x>=0} \\ {- x} & ; & {x < 0} \end{matrix}{{Asin}(x)}\mspace{14mu}{the}\mspace{14mu}{trigonometric}\mspace{14mu}{inverse}\mspace{14mu}{sine}\mspace{14mu}{function}},{{{operating}\mspace{14mu}{on}\mspace{14mu}{an}\mspace{14mu}{argument}\mspace{14mu} x\mspace{14mu}{that}\mspace{14mu}{is}\mspace{14mu}{in}\mspace{14mu}{the}\mspace{14mu}{range}{\mspace{11mu}\;}{of}} - {1.0\mspace{14mu}{to}\mspace{14mu} 1.0}},{inclusive},{{{with}\mspace{14mu}{an}\mspace{14mu}{output}\mspace{14mu}{value}\mspace{14mu}{in}\mspace{14mu}{the}\mspace{14mu}{range}\mspace{14mu}{of}} - {{\pi \div 2}\mspace{14mu}{to}\mspace{14mu}{\pi \div 2}}},{inclusive},{{in}\mspace{14mu}{units}\mspace{14mu}{of}\mspace{14mu}{radians}{{Atan}(x)}\mspace{14mu}{the}\mspace{14mu}{trigonometric}\mspace{14mu}{invere}\mspace{14mu}{tangent}\mspace{14mu}{function}},{{operating}{\mspace{11mu}\;}{on}\mspace{14mu}{an}\mspace{14mu}{argument}\mspace{14mu} x},{{{with}\mspace{14mu}{an}\mspace{14mu}{output}\mspace{14mu}{value}\mspace{14mu}{in}{the}\mspace{14mu}{range}\mspace{14mu}{of}}\mspace{14mu} - {{\pi \div 2}\mspace{14mu}{to}\mspace{14mu}{\pi \div 2}}},{inclusive},{{{in}\mspace{14mu}{units}\mspace{14mu}{of}\mspace{14mu}{radians}{Atan}\; 2\left( {y,x} \right)} = \left\{ {{\begin{matrix} {{Atan}\left( \frac{y}{x} \right)} & ; & {x > 0} \\ {{{Atan}\left( \frac{y}{x} \right)} + \pi} & ; & {{x < 0}\&\&{y>=0}} \\ {{{Atan}\left( \frac{y}{x} \right)} - \pi} & ; & {{x < 0}\&\&{y < 0}} \\ {+ \frac{\pi}{2}} & ; & {{x==0}\&\&{y>=0}} \\ {- \frac{\pi}{2}} & ; & {otherwise} \end{matrix}{{Ceil}(x)}\mspace{14mu}{the}\mspace{14mu}{smallest}\mspace{14mu}{interger}\mspace{14mu}{greater}\mspace{14mu}{than}\mspace{14mu}{or}\mspace{14mu}{equal}\mspace{14mu}{to}\mspace{14mu}{x.{Clip}}\; 1_{Y}(x)} = {{{Clip}\; 3\left( {0,{\left( {1 ⪡ {BitDepth}_{Y}} \right) - 1},x} \right){Clip}\; 1_{C}(x)} = {{{Clip}\; 3\left( {0,{\left( {1 ⪡ {BitDepth}_{C}} \right) - 1},x} \right){Clip}\; 3\left( {x,y,z} \right)} = \left\{ {{\begin{matrix} x & ; & {z < x} \\ y & ; & {z > y} \\ z & ; & {otherwise} \end{matrix}{{Cos}(x)}\mspace{14mu}{the}\mspace{14mu}{trigonometric}\mspace{14mu}{cosine}\mspace{14mu}{function}\mspace{14mu}{operating}\mspace{14mu}{on}\mspace{14mu}{an}\mspace{14mu}{argument}\mspace{14mu} x\mspace{14mu}{in}{\mspace{11mu}\;}{units}\mspace{14mu}{of}\mspace{14mu}{{radians}.{{Floor}(x)}}\mspace{14mu}{the}\mspace{14mu}{largest}\mspace{14mu}{integer}\mspace{14mu}{less}\mspace{14mu}{than}\mspace{14mu}{or}\mspace{14mu}{equal}\mspace{14mu}{to}\mspace{14mu}{x.{{GetCurrMsb}\left( {a,b,c,d} \right)}}} = \left\{ {{\begin{matrix} {c + d} & ; & {{b - a}>={d/2}} \\ {c - d} & ; & {{a - b} > {d/2}} \\ c & ; & {otherwise} \end{matrix}{{Ln}(x)}\mspace{14mu}{the}\mspace{14mu}{natural}\mspace{14mu}{logarithm}\mspace{14mu}{of}\mspace{14mu} x\mspace{14mu}{\left( {{{the}\mspace{14mu}{base}\text{-}e\mspace{14mu}{logarithm}},{{where}\mspace{14mu} e\mspace{14mu}{is}\mspace{14mu}{the}\mspace{14mu}{natural}{\mspace{11mu}\;}{logarithm}\mspace{14mu}{base}\mspace{14mu}{constant}\mspace{14mu} 2.718281828\mspace{14mu}\ldots}}\mspace{14mu} \right).{Log}}\; 2(x)\mspace{14mu}{the}\mspace{14mu}{base}\text{-}2\mspace{14mu}{logarithm}\mspace{14mu}{of}\mspace{14mu}{x.{Log}}\; 10(x)\mspace{14mu}{the}\mspace{14mu}{base}\text{-}10\mspace{14mu}{logarithm}\mspace{14mu}{of}\mspace{14mu}{x.{{Min}\left( {x,y} \right)}}} = \left\{ {{\begin{matrix} x & ; & {x<=y} \\ y & ; & {x > y} \end{matrix}{{Max}\left( {x,y} \right)}} = \left\{ {{\begin{matrix} x & ; & {x>=y} \\ y & ; & {x < y} \end{matrix}{{Round}(x)}} = {{{{Sign}(x)}*{{Floor}\left( {{{Abs}(x)} + 0.5} \right)}{{Sign}(x)}} = \left\{ {{\begin{matrix} 1 & ; & {x > 0} \\ 0 & ; & {x==0} \\ {- 1} & ; & {x < 0} \end{matrix}{{Sin}(x)}\mspace{14mu}{the}\mspace{14mu}{trigonometric}\mspace{14mu}{sine}\mspace{14mu}{function}\mspace{14mu}{operating}\mspace{14mu}{on}\mspace{14mu}{an}\mspace{14mu}{argument}\mspace{14mu} x\mspace{14mu}{in}\mspace{14mu}{units}\mspace{14mu}{of}\mspace{14mu}{radians}{{Sqrt}(x)}} = {{\sqrt{x}{{Swap}\left( {x,y} \right)}} = {\left( {y,x} \right){{Tan}(x)}\mspace{14mu}{the}\mspace{14mu}{trigonometric}\mspace{14mu}{tangent}\;{function}\mspace{14mu}{operating}\mspace{14mu}{on}\mspace{14mu}{an}\mspace{14mu}{argument}\mspace{14mu} x\mspace{14mu}{in}\mspace{14mu}{units}\mspace{14mu}{of}\mspace{14mu}{radians}}}} \right.}} \right.} \right.} \right.} \right.}}} \right.}} \right.$

Order of Operation Precedence

When an order of precedence in an expression is not indicated explicitly by use of parentheses, the following rules apply:

-   -   Operations of a higher precedence are evaluated before any         operation of a lower precedence.     -   Operations of the same precedence are evaluated sequentially         from left to right.

The table below specifies the precedence of operations from highest to lowest; a higher position in the table indicates a higher precedence.

For those operators that are also used in the C programming language, the order of precedence used in this Specification is the same as used in the C programming language.

TABLE Operation precedence from highest (at top of table) to lowest (at bottom of table) operations (with operands x, y, and z) ″x + +″, ″x − −″ ″!x″, ″−x″ (as a unary prefix operator) x^(y) ${{\,^{''}x}*y^{''}},{{\,^{''}x}\text{/}y^{''}},{{\,^{''}x} \div y^{''}},\frac{{\;^{''}x^{''}\quad}\quad}{y},{{\,^{''}x}\mspace{14mu}\%\mspace{14mu} y^{''}}$ ${{\,^{''}x} + y^{''}},^{''}{x - {y^{''}\left( {{as}\mspace{14mu} a\mspace{14mu}{two}\text{-}{argument}\mspace{14mu}{operator}} \right)}},^{''}{\sum\limits_{i = x}^{y}{f(i)}^{''}}$ ″x << y″, ″x >> y″ ″x < y″, ″x <= y″, ″x > y″, ″x >= y″ ″x = = y″, ″x != y″ ″x & y″ ″x | y″ ″x & & y″ ″x | | y″ ″x ? y : z″ ″x . . . y″ ″x = y″, ″x + = y″, ″x − = y″

Text Description of Logical Operations

In the text, a statement of logical operations as would be described mathematically in the following form:

 if( condition 0 )   statement 0  else if( condition 1 )   statement 1  ...  else /* informative remark on remaining condition */   statement n may be described in the following manner:   ... as follows / ... the following applies:   — If condition 0, statement 0   — Otherwise, if condition 1, statement 1   — ...   — Otherwise (informative remark on remaining condition),     statement n

Each “If . . . Otherwise, if . . . Otherwise, . . . ” statement in the text is introduced with “ . . . as follows” or “ . . . the following applies” immediately followed by “If . . . ”. The last condition of the “If . . . Otherwise, if . . . Otherwise, . . . ” is always an “Otherwise, . . . ”. Interleaved “If . . . Otherwise, if . . . Otherwise, . . . ” statements can be identified by matching “ . . . as follows” or “ . . . the following applies” with the ending “Otherwise, . . . ”.

In the text, a statement of logical operations as would be described mathematically in the following form:

 if( condition 0a && condition 0b )   statement 0  else if( condition 1a ∥ condition 1b )   statement 1  ...  else   statement n may be described in the following manner:  ... as follows / ... the following applies:  — If all of the following conditions are true, statement 0:    — condition 0a    — condition 0b  — Otherwise, if one or more of the following conditions are true,    statement 1:    — condition 1a    — condition 1b  — ...  — Otherwise, statement n

In the text, a statement of logical operations as would be described mathematically in the following form:

  if( condition 0 )  statement 0 if( condition 1)  statement 1 may be described in the following manner:

When condition 0, statement 0

When condition 1, statement 1.

Although embodiments of the invention have been primarily described based on video coding, it should be noted that embodiments of the coding system 10, encoder 20 and decoder 30 (and correspondingly the system 10) and the other embodiments described herein may also be configured for still picture processing or coding, i.e. the processing or coding of an individual picture independent of any preceding or consecutive picture as in video coding. In general only inter-prediction units 244 (encoder) and 344 (decoder) may not be available in case the picture processing coding is limited to a single picture 17. All other functionalities (also referred to as tools or technologies) of the video encoder 20 and video decoder 30 may equally be used for still picture processing, e.g. residual calculation 204/304, transform 206, quantization 208, inverse quantization 210/310, (inverse) transform 212/312, partitioning 262/362, intra-prediction 254/354, and/or loop filtering 220, 320, and entropy coding 270 and entropy decoding 304.

Embodiments, e.g. of the encoder 20 and the decoder 30, and functions described herein, e.g. with reference to the encoder 20 and the decoder 30, may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on a computer-readable medium or transmitted over communication media as one or more instructions or code and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to a tangible medium such as data storage media, or communication media including any medium that facilitates transfer of a computer program from one place to another, e.g., according to a communication protocol. In this manner, computer-readable media generally may correspond to (1) tangible computer-readable storage media which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementation of the techniques described in this disclosure. A computer program product may include a computer-readable medium.

By way of example, and not limiting, such computer-readable storage media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but are instead directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

Instructions may be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and/or software modules configured for encoding and decoding, or incorporated in a combined codec. Also, the techniques could be fully implemented in one or more circuits or logic elements.

The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware units. Rather, as described above, various units may be combined in a codec hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware. 

1. A method of video coding implemented by a decoding device, comprising: determining that a current coding block of a picture in a video is processed by using an intra sub-partition (ISP) coding mode; when the current coding block is processed by using ISP coding mode, determining whether a width of a current transform block is larger than or equal to a first threshold or not, and whether the width of the current transform block is smaller than or equal to a second threshold or not, the current transform block corresponding to the current coding block; and when the width of the current transform block is larger than or equal to the first threshold and the width of the current transform block is smaller than or equal to the second threshold, performing a transform process on the current transform block to generate transformed values for the current transform block, based on a transform core discrete sine transform 7 (DST 7) for a horizontal direction transform of the transform process.
 2. The method of claim 1, further comprising: when the width of the current transform block is smaller than the first threshold, or when the width of the current transform block is larger than the second threshold, performing the transform process on the current transform block to generate the transformed values for the current transform block based on a transform core discrete cosine transform 2 (DCT2) for the horizontal direction transform of the transform process.
 3. The method of claim 2, further comprising: determining that a prediction mode of the current coding block is an intra prediction mode by obtaining a value of a syntax for the current coding block from a bit stream of the video, wherein the value of the syntax for the current coding block indicates the prediction mode of the current coding block is the intra prediction mode, and wherein the transform process is performed further based on the prediction mode of the current coding block being the intra prediction mode independent of a specific intra prediction mode.
 4. The method of claim 3, wherein the value of the syntax for the current coding block does not indicate a specific prediction mode of the intra prediction mode for the current coding block.
 5. The method of claim 1, wherein the method further comprises: determining that a prediction mode of the current coding block is an intra prediction mode by obtaining a value of a syntax for the current coding block from a bit stream of the video, wherein the value of the syntax for the current coding block indicates the prediction mode of the current coding block is the intra prediction mode, and wherein the transform process is performed further based on the prediction mode being the intra prediction mode independent of a specific intra prediction mode of the current coding block.
 6. The method of claim 5, wherein the value of the syntax for the current coding block does not indicate a specific prediction mode of the intra prediction mode for the current coding block.
 7. A method of video coding implemented by a decoding device, comprising: determining that a current coding block of a picture in a video is processed by using an intra sub-partition (ISP) coding mode; when the current coding block is processed by using the ISP coding mode, determining whether a height of a current transform block is larger than or equal to a third threshold or not, and whether the height of the current transform block is smaller than or equal to a fourth threshold or not, the current transform block corresponding to the current coding block; and when the height of the current transform block is larger than or equal to the third threshold and smaller than or equal to the fourth threshold, performing a transform process on the current transform block to generate transformed values for the current transform block based on a transform core discrete sine transform 7 (DST 7) for a vertical direction transform of the transform process.
 8. The method of claim 7, further comprising: when the height of the current transform block is smaller than the third threshold, or when the height of the current transform block is larger than the fourth threshold, performing the transform process on the current transform block to generate the transformed values for the current transform block based on a transform core discrete cosine transform 2 (DCT 2) for the vertical direction transform of the transform process.
 9. The method of claim 8, further comprising: determining that a prediction mode of the current coding block is an intra prediction mode by obtaining a value of a syntax for the current coding block from a bit stream of the video, wherein the value of the syntax for the current coding block indicates the prediction mode of the current coding block is the intra prediction mode, and wherein the transform process is performed further based on the prediction mode of the current coding block being the intra prediction mode independent of a specific intra prediction mode.
 10. The method of claim 9, wherein the value of the syntax for the current coding block does not indicate a specific prediction mode of the intra prediction mode for the current coding block.
 11. The method of claim 7, further comprising: determining that a prediction mode of the current coding block is an intra prediction mode by obtaining a value of a syntax for the current coding block, wherein the value of the syntax for the current coding block indicates the prediction mode of the current coding block is the intra prediction mode, and wherein the transform process is performed further based on the prediction mode of the current coding block being the intra prediction mode independent of a specific intra prediction mode.
 12. The method of claim 11, wherein the value of the syntax for the current coding block does not indicate a specific prediction mode of the intra prediction mode for the current coding block.
 13. A method of video coding implemented by a decoding device, comprising: determining, when one or more conditions are satisfied, the one or more conditions comprising a multiple transform selection (MTS) scheme is unavailable for a current coding block of a picture in a video, whether a width of a current transform block is larger than or equal to a first threshold or not, and whether the width of the current transform block is smaller than or equal to a second threshold or not, the current transform block corresponding to the current coding block; and when the width of the current transform block is larger than or equal to the first threshold and smaller than or equal to the second threshold, performing a transform process on the current transform block to generate transformed values for the current transform block based on a transform core discrete sine transform 7 (DST 7) for a horizontal direction transform of the transform process.
 14. The method of claim 13, further comprising: when the width of the current transform block is smaller than the first threshold, or when the width of the current transform block is larger than the second threshold, performing the transform process on the current transform block to generate the transformed values for the current transform block based on a transform core discrete cosine transform 2 (DCT 2) for the horizontal direction transform of the transform process.
 15. A method of video coding implemented by a decoding device, comprising: determining, when one or more conditions are satisfied, the one or more conditions comprising a multiple transform selection (MTS) scheme is unavailable for a current coding block of a picture in a video, whether a height of a current transform block is larger than or equal to a third threshold or not, and whether the height of the current transform block is smaller than or equal to a fourth threshold or not, the current transform block corresponding to the current coding block; and when the height of the current transform block is larger than or equal to the third threshold and smaller than or equal to the fourth threshold, performing a transform process on the current transform block to generate transformed values for the current transform block based on a transform core discrete sine transform 7 (DST 7) for a vertical direction transform of the transform process.
 16. The method of claim 15, further comprising: when the height of the current transform block is smaller than the third threshold, or when the height of the current transform block is larger than the fourth threshold, performing the transform process on the current transform block to generate the transformed values for the current transform block based on a transform core discrete cosine transform 2 (DCT 2) for the vertical direction transform of the transform process.
 17. A decoder, comprising: one or more processors; and a non-transitory computer-readable storage medium coupled to the processors and storing programming for execution by the processors, wherein the programming, when executed by the processors, configures the decoder to perform operations comprising: determining that a current coding block of a picture in a video is processed by using an intra sub-partition (ISP) coding mode; when the current coding block is processed by using the ISP coding mode, determining whether a width of a current transform block is larger than or equal to a first threshold or not, and whether the width of the current transform block is smaller than or equal to a second threshold or not, the current transform block corresponding to the current coding block; and when the width of the current transform block is larger than or equal to the first threshold and smaller than or equal to the second threshold, performing a transform process on the current transform block to generate transformed values for the current transform block based on a transform core discrete sine transform 7 (DST 7) for a horizontal direction transform of the transform process.
 18. The decoder of claim 17, wherein the operations further comprise: when the width of the current transform block is smaller than the first threshold, or when the width of the current transform block is larger than the second threshold, performing the transform process on the current transform block to generate the transformed values for the current transform block based on a transform core discrete cosine transform 2 (DCT2) for the horizontal direction transform of the transform process.
 19. The decoder of claim 17, wherein the operations further comprises: determining that a prediction mode of the current coding block is an intra prediction mode by obtaining a value of a syntax for the current coding block from a bit stream of the video, wherein the value of the syntax for the current coding block indicates the prediction mode of the current coding block is the intra prediction mode, and wherein the transform process is performed further based on the prediction mode of the current coding block being the intra prediction mode independent of a specific intra prediction mode.
 20. The decoder of claim 19, wherein the value of the syntax for the current coding block does not indicate a specific prediction mode of the current coding block. 